High-speed four-phase twenty-five percent duty clock generator

1 . A four-phase clock generator comprising:

a de-assertion network including four MOS (metal-oxide semiconductor) transistors of a first conductivity type, each configured in a common-source arrangement and interconnected in a ring topology to sequentially and cyclically de-assert a first phase, a second phase, a third phase, and a fourth phase of a four-phase output clock, respectively;

a first alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the first phase and the third phase of the four-phase output clock;

a second alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the second phase and the fourth phase of the four-phase output clock; and

an assertion network comprising four MOS transistors of a second conductivity type configured to sequentially and cyclically assert the first phase, the second phase, the third phase, and the fourth phase of the four-phase output clock in accordance with four gated clock signals generated by alternately gating a first phase and a second phase of a two-phase input clock using the fourth phase, the first phase, the second phase, and the third phase of the four-phase output clock, respectively,

wherein:

each phase of the four-phase clock is de-asserted by a respective MOS transistor of the first conductivity type in response to assertion of a succeeding phase that connects to a gate of the respective MOS transistor,

the phase of the four-phase clock is asserted by a respective MOS transistor of the second conductivity type in response to de-assertion of a respective gated clock signal generated by a respective clock-gating network, and

the respective clock-gating network comprising a stack up of two MOS transistors of the first conductivity type controlled by the respective phase of the two-phase input clock and a preceding phase of the phase of the four-phase clock, respectively, and a MOS transistor of the second conductivity type controlled by the respective phase of the two-phase input clock.

2 . The four-phase clock generator of claim 1 , wherein the MOS transistor of the first conductivity type is a NMOS (n-channel metal-oxide semiconductor) transistor, while the MOS transistor of the second conductivity type is a PMOS (p-channel metal-oxide semiconductor) transistor.

3 . The four-phase clock generator of claim 1 , wherein the MOS transistor of the first conductivity type is a PMOS (p-channel metal-oxide semiconductor) transistor, while the MOS transistor of the second conductivity type is a NMOS (n-channel metal-oxide semiconductor) transistor.

4 . The four-phase clock of claim 1 further comprising a jolting circuit configured to forcefully assert at least one of the first phase, the second phase, the third phase, and the fourth phase of the four-phase clock for a brief interval in a one-time manner.

5 . The four-phase clock of claim 4 , wherein the jolting circuit comprises a MOS transistor of the second conductivity type configured to forcefully assert one of the first phase, the second phase, the third phase, and the fourth phase of the four-phase clock in response to a jolt signal.

6 . The four-phase clock of claim 5 , wherein the jolt signal is generated by a power-on reset circuit.

7 . The four-phase clock of claim 5 , wherein the MOS transistor of the first conductivity type is a NMOS (n-channel metal oxide) transistor, the MOS transistor of the second conductivity type is a PMOS (p-channel metal oxide) transistor, and the jolt signal is generated by performing a logical OR operation on the first phase, the second phase, the third phase, and the fourth phase of the four-phase clock so that the jolt signal is high unless all of the first phase, the second phase, the third phase, and the fourth phase of the four-phase clock are low.