Semiconductor devices and multi-bit flip-flop circuits having an asymmetrical row structure
A semiconductor device includes a plurality of first functional blocks formed in a plurality of first cell rows, and a plurality of second functional blocks formed in a plurality of second cell rows. The first functional blocks are configured to provide a first predetermined function. The second functional blocks are configured to provide a second predetermined function which is the same as the first predetermined function. The first cell rows and the second cell rows have at least one different physical property. The plurality of first functional blocks and the plurality of second functional blocks are placed in a predetermined arrangement to sequentially generate a bit sequence, the predetermined arrangement having a sinuous shape or a serpentine shape.
1 . A semiconductor device, comprising:
a plurality of cell rows, wherein the plurality of cell rows comprise a plurality of first cell rows and a plurality of second cell rows;
a plurality of first functional blocks, respectively formed in the plurality of first cell rows and configured to provide a first predetermined function; and
a plurality of second functional blocks, respectively formed in the plurality of second cell rows and configured to provide a second predetermined function which is the same as the first predetermined function,
wherein the plurality of first cell rows and the plurality of second cell rows have at least one different physical property, and the plurality of first functional blocks and the plurality of second functional blocks are placed in a predetermined arrangement to sequentially generate a bit sequence having a plurality of bits respectively generated by the plurality of first functional blocks and the plurality of second functional blocks, the predetermined arrangement having a sinuous shape or a serpentine shape, wherein an output of a first functional block of the plurality of first functional blocks in a first cell row is input to another first functional block of the plurality of first functional blocks in a same first cell row or input to a second functional block of the plurality of second functional blocks in a second cell row directly adjacent to the first cell row, and an output of a second functional block of the plurality of second functional blocks in a second cell row is input to another second functional block of the plurality of second functional blocks in a same second cell row or input to a first functional block of the plurality of first functional blocks in a first cell row directly adjacent to the second cell row.
2 . The semiconductor device of claim 1 , wherein each first functional block and each second functional block is a single-bit flip-flop circuit.
3 . The semiconductor device of claim 1 , wherein a height of the first cell rows is different from a height of the second cell rows.
4 . The semiconductor device of claim 1 , wherein a driving capability of the first cell rows is different from a driving capability of the second cell rows, and wherein the driving capability of the first/second cell rows is determined by at least one of a device width, a fin number and a finger number of a transistor device on the first/second cell row.
5 . The semiconductor device of claim 1 , wherein the plurality of first cell rows and the plurality of second cell rows are arranged in an interleaved manner.
6 . A multi-bit flip-flop circuit, comprising:
a plurality of first cell rows;
a plurality of second cell rows; and
a plurality of single-bit flip-flop circuits, comprising:
a first single-bit flip-flop circuit, formed in one of the first cell rows;
a second single-bit flip-flop circuit, formed in one of the second cell rows;
a third single-bit flip-flop circuit, formed in said one of the first cell rows; and
a fourth single-bit flip-flop circuit, formed in said one of the second cell rows;
wherein the plurality of first cell rows and the plurality of second cell rows have at least one different physical property, and the plurality of single-bit flip-flop circuits are placed in a predetermined arrangement to sequentially generate a bit sequence having a plurality of bits respectively generated by the plurality of single-bit flip-flop circuits, the predetermined arrangement having a sinuous shape or a serpentine shape, wherein an output of a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a first cell row is input to another single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a same first cell row or input to a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a second cell row directly adjacent to the first cell row, and an output of a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a second cell row is input to another single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a same second cell row or input to a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a first cell row directly adjacent to the second cell row.
7 . The multi-bit flip-flop circuit of claim 6 , wherein a height of one of the first cell rows is different from a height of one of the second cell rows.
8 . The multi-bit flip-flop circuit of claim 6 , wherein a driving capability of one of the first cell rows is different from a driving capability of one of the second cell rows, and wherein the driving capability of said one of the first/second cell rows is determined by at least one of a device width, a fin number and a finger number of a transistor device on said one of the first/second cell rows.
9 . The multi-bit flip-flop circuit of claim 6 , wherein the plurality of single-bit flip-flop circuits further comprises:
a fifth single-bit flip-flop circuit, formed in another of the first cell rows;
a sixth single-bit flip-flop circuit, formed in another of the second cell rows;
a seventh single-bit flip-flop circuit, formed in said another of the first cell rows; and
an eighth single-bit flip-flop circuit, formed in said another of the second cell rows.
10 . The multi-bit flip-flop circuit of claim 6 , wherein at least one circuit sub-unit in the first single-bit flip-flop circuit and at least one circuit sub-unit in the second single-bit flip-flop circuit have the same function but have different circuitry.
11 . The multi-bit flip-flop circuit of claim 6 , wherein the plurality of first cell rows and the plurality of second cell rows are arranged in an interleaved manner.
12 . A multi-bit flip-flop circuit, comprising:
a plurality of first cell rows;
a plurality of second cell rows; and
a plurality of single-bit flip-flop circuits, wherein a first portion of the plurality of single-bit flip-flop circuits are formed in the first cell rows and a second portion of the plurality of single-bit flip-flop circuits are formed in the second cell rows;
wherein the first cell rows and the second cell rows have at least one different physical property, and the plurality of single-bit flip-flop circuits are placed in a predetermined arrangement to sequentially generate a bit sequence having a plurality of bits respectively generated by the plurality of single-bit flip-flop circuits, the predetermined arrangement having a sinuous shape or a serpentine shape, wherein an output of a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a first cell row is input to another single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a same first cell row or input to a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a second cell row directly adjacent to the first cell row, and an output of a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a second cell row is input to another single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a same second cell row or input to a single-bit flip-flop circuit of the plurality of single-bit flip-flop circuits in a first cell row directly adjacent to the second cell row.
13 . The multi-bit flip-flop circuit of claim 12 , wherein the plurality of first cell rows at least comprise a first first cell row and a second first cell row, the plurality of second cell rows at least comprise a first second cell row and a second second cell row, and an arrangement of the plurality of first cell rows and the plurality of second cell rows from a top to a bottom of a layout is the first first cell row, the first second cell row, the second first cell row and the second second cell row.
14 . The multi-bit flip-flop circuit of claim 13 , wherein the plurality of single-bit flip-flop circuits comprises:
a first single-bit flip-flop circuit, formed in the first first cell row;
a second single-bit flip-flop circuit, formed in the first first cell row, a third single-bit flip-flop circuit, formed in the first second cell row;
a fourth single-bit flip-flop circuit, formed in the first second cell row;
a fifth single-bit flip-flop circuit, formed in the second first cell row;
a sixth single-bit flip-flop circuit, formed in the second first cell row;
a seventh single-bit flip-flop circuit, formed in the second second cell row; and
an eight single-bit flip-flop circuit, formed in the second second cell row.
15 . The multi-bit flip-flop circuit of claim 12 , wherein the plurality of first cell rows at least comprise a first first cell row and a second first cell row, the plurality of second cell rows at least comprise a first second cell row and a second second cell row, and an arrangement of the plurality of first cell rows and the plurality of second cell rows from a top to a bottom of a layout is the first first cell row, the first second cell row, the second second cell row and the second first cell row.
16 . The multi-bit flip-flop circuit of claim 12 , wherein the plurality of first cell rows at least comprise a first first cell row and a second first cell row, the plurality of second cell rows at least comprise a first second cell row and a second second cell row, and an arrangement of the plurality of first cell rows and the plurality of second cell rows from a top to a bottom of a layout is the first first cell row, the second first cell row, the first second cell row and the second second cell row.
17 . The multi-bit flip-flop circuit of claim 12 , wherein the first portion of the plurality of single-bit flip-flop circuits and the second portion of the plurality of single-bit flip-flop circuits have the same function but have different circuitry.
18 . The multi-bit flip-flop circuit of claim 12 , wherein at least one circuit sub-unit in any single-bit flip-flop circuit of the first portion of the plurality of single-bit flip-flop circuits and at least one circuit sub-unit in any single-bit flip-flop circuit of the second portion of the plurality of single-bit flip-flop circuits have the same function but have different circuitry.