Metastability-tolerant droop response apparatus and method
An integrated circuit (IC) chip includes a voltage supply circuit to provide a supply voltage. A droop detection circuit couples to the voltage supply circuit to detect a reduction in the supply voltage and to generate a droop detection signal based on the reduction in the supply voltage. Asynchronous response circuitry couples to the droop detection circuit. The asynchronous response circuitry is responsive to the droop detection signal to generate a droop response signal to reduce a frequency of a clock signal from a nominal operating frequency to a reduced frequency.
1 . An integrated circuit (IC) chip, comprising:
a system clock to generate a clock signal, the system clock comprising a digitally-controlled oscillator (DCO) circuit;
a voltage supply circuit to provide a supply voltage;
a droop detection circuit coupled to the voltage supply circuit to detect a reduction in the supply voltage and to generate a droop detection signal based on the reduction in the supply voltage;
asynchronous response circuitry coupled to the droop detection circuit, the asynchronous response circuitry being asynchronous to the clock signal and responsive to the droop detection signal to generate a droop response signal to reduce a frequency of the clock signal from a nominal operating frequency to a reduced frequency; and
wherein the DCO is responsive to application of a first digital code to generate the nominal operating frequency and responsive to application of a reduced digital code corresponding to the droop response signal to generate the reduced frequency.
2 . The IC chip of claim 1 , wherein:
the asynchronous response circuitry includes circuitry to generate the reduced digital code.
3 . The IC chip of claim 2 , wherein:
the circuitry to generate the reduced digital code includes bit shift selection circuitry to generate the reduced digital code in response to receiving a shift signal based on the droop detection signal.
4 . The IC chip of claim 2 , wherein:
the first digital code and the reduced digital code are thermometer-encoded.
5 . The IC chip of claim 1 , further comprising:
a droop response controller to receive a copy of the droop detection signal and to generate a reduce signal; and
a loop filter coupled to the droop response controller and responsive to the reduce signal to internally configure a resulting binary code to correspond to the reduced digital code.
6 . The IC chip of claim 1 , wherein:
the DCO includes a delay circuit responsive to the reduced digital code to reduce a current draw parameter, and wherein the frequency of the clock signal is based on the current draw parameter.
7 . A voltage droop response circuit, comprising:
a droop detection circuit for coupling to a voltage supply circuit that generates a supply voltage, the droop detection circuit to detect a reduction in the supply voltage and to generate a droop detection signal based on the reduction in the supply voltage; and
asynchronous response circuitry coupled to the droop detection circuit, the asynchronous response circuitry being asynchronous to a clock signal of a system clock and responsive to the droop detection signal to generate a droop response signal to reduce a frequency of the clock signal from a nominal operating frequency to a reduced frequency; and
wherein the system clock comprises a digitally-controlled oscillator (DCO) circuit to generate the clock signal, the DCO being responsive of a first digital code to generate the nominal operating frequency, and responsive to application of a reduced digital code corresponding to the droop response signal to generate the reduced frequency.
8 . The voltage droop response circuit of claim 7 , wherein:
the asynchronous response circuitry comprises circuitry to generate the reduced digital code.
9 . The voltage droop response circuit of claim 8 , wherein:
the circuitry to generate the reduced digital code comprises bit shift selection circuitry to generate the reduced digital code in response to receiving a shift signal based on the droop detection signal.
10 . The voltage droop response circuit of claim 8 , wherein:
the first digital code and the reduced digital code are thermometer-encoded.
11 . The voltage droop response circuit of claim 7 , further comprising:
a droop response controller to receive a copy of the droop detection signal and to generate a reduce signal; and
a loop filter coupled to the droop response controller and responsive to the reduce signal to internally configure a resulting binary code to correspond to the reduced digital code.
12 . The voltage droop response circuit of claim 7 , wherein:
the DCO includes a delay circuit responsive to the reduced digital code to reduce a current draw parameter, and wherein the frequency of the clock signal is based on the current draw parameter.
13 . A method of operation in an integrated circuit (IC) chip, the method comprising:
providing a supply voltage with a voltage supply circuit;
generating a clock signal with a system clock that comprises a digitally-controlled oscillator (DCO) circuit,
responding to application of a first digital code with the DCO to generate a nominal operating frequency,
detecting a reduction in the supply voltage with a droop detection circuit and generating a droop detection signal based on the reduction in the supply voltage;
asynchronously responding to the droop detection signal with an asynchronous response circuit that is asynchronous to the clock signal of the system clock, the asynchronously responding including generating a droop response signal to reduce a frequency of the clock signal from the nominal operating frequency to a reduced frequency; and
responding to application of a reduced digital code corresponding to the droop response signal to generate the reduced frequency.
14 . The method of claim 13 , further comprising:
generating the reduced digital code with bit shift selection circuitry in response to receiving a shift signal based on the droop detection signal.
15 . The method of claim 13 , further comprising:
thermometer-encoding the first digital code and the reduced digital code.
16 . The method of claim 13 , further comprising:
receiving a copy of the droop detection signal with a droop response controller;
generating a reduce signal with the droop response controller; and
internally configuring a resulting binary code with a loop filter to correspond to the reduced digital code.
17 . The method of claim 13 , wherein:
reducing a current draw parameter in response to the reduced digital code with a delay circuit; and
wherein the frequency of the clock signal is based on the current draw parameter.