High speed current mode mux with inductive input
In one embodiment, the disclosure relates to a method of adjusting a current steering multiplexer. The method includes providing a first subDAC comprising a first current mode output; providing a second subDAC comprising a second current mode output; and providing a current mode multiplexer. The method may also include clocking the current mode multiplexer using a first clock signal having a first frequency; clocking the first subDAC using a second clock signal having a second frequency; clocking the second subDAC using the second clock signal, wherein the second frequency is twice the first frequency; and combining currents from the first current mode output and the second current mode output.
1 . A system comprising:
a 2:1 multiplexer (MUX) having a first input and a second input;
a first sub-digital-to-analog (subDAC) having a first output;
a second subDAC having a second output; a first transmission line electrically coupling the first subDAC to the first input;
a ground shield for the first transmission line, wherein a first loop inductor is integrated into the ground shield for the first transmission line;
a second transmission line electrically coupling the second subDAC to the second input; and
a ground shield for the second transmission line, wherein a second loop inductor is integrated into the ground shield for the second transmission line.
2 . The system of claim 1 wherein the MUX selectively interleaves the first output of the first subDAC and the second output of the second subDAC.
3 . The system of claim 1 , wherein
the first transmission line is coupled to a first switch in the MUX, and
wherein the second transmission line is coupled to a second switch in the MUX.
4 . The system of claim 3 , wherein the first and second loop inductors are sized such that parasitic capacitances of the first switch and the second switch are substantially absorbed by the first and second transmission lines.
5 . The system of claim 1 , wherein the first and second loop inductors each comprises one or more half-loops.
6 . The system of claim 1 , wherein the MUX provides termination of input signals from the first subDAC and the second subDAC such that substantially all current from the first subDAC and the second subDAC appear at an output of the MUX.
7 . The system of claim 1 , wherein the first transmission line comprises a first pair of differential current-mode conductors that connect the first subDAC to the MUX, wherein the first pair of differential current-mode conductors extends over the first loop inductor,
wherein the second transmission line comprises a second pair of differential current-mode conductors that connect the second subDAC to the MUX, wherein the second pair of differential current-mode conductors extends over the second loop inductor.
8 . The system of claim 7 , wherein the first loop inductor is disposed on a first end of the ground shield in the first transmission line where the first pair of differential current-mode conductors connect to the MUX,
wherein the second loop inductor is disposed on a first end of the ground shield in the second transmission line where the second pair of differential current-mode conductors connect to the MUX.
9 . The system of claim 8 , wherein a second end of the ground shield in the first transmission line does not have a loop, and
wherein a second end of the ground shield in the second transmission line does not have a loop.
10 . The system of claim 7 , further comprising:
a first programmable capacitor disposed over the first pair of differential current-mode conductors and the ground shield in the first transmission line; and
a second programmable capacitor disposed over the second pair of differential current-mode conductors and the ground shield in the second transmission line.
11 . The system of claim 10 , further comprising:
a third programmable capacitor disposed over the first pair of differential current-mode conductors and the ground shield in the first transmission line, wherein the first and third programmable capacitors are disposed at different locations on the first transmission line; and
a fourth programmable capacitor disposed over the second pair of differential current-mode conductors and the ground shield in the second transmission line, wherein the second and fourth programmable capacitors are disposed at different locations on the second transmission line.
12 . The system of claim 11 , wherein the first and third programmable capacitors are disposed over portions of the ground shield in the first transmission line that do not include the first loop inductor, and
wherein the second and fourth programmable capacitors are disposed over portions of the ground shield in the second transmission line that do not include the second loop inductor.