Device and method for bulk induced pre-emphasis technique in current mode transmitter for high speed links

1 . An integrated circuit, comprising:

an input data source;

a current mode transmitter coupled to the input data source and including:

a primary driver including a first driver switch;

a secondary driver including a second driver switch;

a delay circuit coupled between the input data source and the secondary driver;

a transition detector having:

a first input coupled to an input of the primary driver;

a second input coupled to an input of the secondary driver;

an output coupled to a bulk terminal of the first driver switch and to a bulk terminal of the second driver switch;

a first predriver circuit coupled between the input data source and the primary driver; and

a second predriver circuit coupled between the delay circuit and secondary driver, wherein the input data source provides a data stream to the input of the primary driver and to an input of the delay circuit, wherein the delay circuit provides, to the input of the secondary driver, a delayed data stream delayed relative to the data stream.

2 . The integrated circuit of claim 1 , wherein the transition detector includes a logic gate.

3 . The integrated circuit of claim 2 , wherein the logic gate is an XOR gate.

4 . The integrated circuit of claim 1 , wherein the transition detector outputs a high supply voltage to the bulk terminals of the first and second driver switches when a value of the data stream changes.

5 . The integrated circuit of claim 4 , wherein the transition detector outputs a low supply voltage to the bulk terminals of the first and second driver switches when the value of the data stream does not change.

6 . The integrated circuit of claim 1 , wherein the data input source outputs the data stream in accordance with a clock signal.

7 . The integrated circuit of claim 6 , wherein the delayed data stream is delayed relative to the data stream by a single cycle of the clock signal.

8 . The integrated circuit of claim 1 , wherein the primary driver and the secondary driver collectively provide output data.

9 . An integrated circuit, comprising:

an input data source;

a current mode transmitter including:

a primary driver of a current mode transmitter, the primary driver including an input and a first driver switch having a bulk terminal;

a secondary driver of the current mode transmitter, the secondary driver including an input and a second driver switch having a bulk terminal;

a delay circuit coupled between the input data source and the secondary driver;

a transition detector having:

a first input coupled to an input of the primary driver;

a second input coupled to an input of the secondary driver; and an output coupled to the bulk terminal of the first driver switch and to the bulk terminal of the second driver switch;

a first predriver circuit coupled between the input data source and the primary driver; and

a second predriver circuit coupled between the delay circuit and secondary driver, wherein the input data source provides a data stream to the input of the primary driver and to an input of the delay circuit, wherein the delay circuit provides, to the input of the secondary driver, a delayed data stream delayed relative to the data stream.

10 . The integrated circuit of claim 9 , comprising a transmission line coupled to an output of the primary driver and the secondary driver.

11 . The integrated circuit of claim 10 , wherein the primary driver and the secondary driver are configured to output a data stream onto the transmission line in a current mode scheme.

12 . The integrated circuit of claim 9 , wherein the first driver switch includes a plurality of transistors coupled together in parallel.

13 . A method, comprising:

receiving, from an input data source, a stream of data values at a primary driver of a current mode transmitter;

receiving, with a delay circuit of the current mode transmitter, the stream of data values from the input data source;

providing, to a secondary driver of the current mode transmitter from the delay circuit, a delayed data stream delayed relative to the data stream, the delay circuit being coupled between the input data source and the secondary driver;

receiving the stream of data values at a first input of a transition detector and the delayed stream of data values at a second input of the transition detector;

generating, with the transition detector, a bulk modulation voltage based on the stream of data values; and

supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the primary driver and to a bulk terminal of a second driver switch of the secondary driver, wherein the current mode transmitter includes a first predriver circuit coupled between the input data source and the primary driver and a second predriver circuit coupled between the delay circuit and secondary driver.

14 . The method of claim 13 , wherein the bulk modulation voltage goes high when the stream of data values transitions from high to low or from low to high.

15 . The method of claim 13 , wherein the bulk modulation voltage goes low when the stream of data values does not change for two or more consecutive clock cycles.

16 . The method of claim 13 , comprising driving, with the primary driver, a current having a first value when the bulk modulation signal is low and a second value different than the first value when the bulk modulation signal is high.

17 . The method of claim 16 , wherein the second value is higher than the first value.