Methods and systems of operating a double-sided double-base bipolar junction transistor

1 . A method of operating a switch assembly, the method comprising:

blocking current flow from an upper terminal of the switch assembly to a lower terminal of the switch assembly by a transistor; and then, responsive to assertion of a conduction signal, conducting a first load current from the upper terminal to a lower terminal by:

closing an upper-main FET coupled between the upper terminal and an upper collector-emitter of the transistor;

closing a lower-main FET coupled between a lower collector-emitter of the transistor and the lower terminal;

driving a first turn-on current to an upper base of the transistor from an upper current source; and then

providing a first steady-state current to the upper base from the upper current source, the first steady-state current lower than the first turn-on current,

wherein driving the first turn-on current from the upper current source comprises driving the first turn-on current from an upper power converter based on a first upper feedback derived from an output voltage of the upper power converter, and

wherein providing the first steady-state current from the upper current source comprises providing the first steady-state current from the upper power converter based on a second upper feedback derived from current provided by the upper power converter.

2 . The method of claim 1 further comprising interrupting the first load current by opening the lower-main FET, and then arranging the transistor to block current from the upper terminal to the lower terminal.

3 . The method of claim 2 further comprising:

blocking current flow from the lower terminal to the upper terminal by the transistor; and then responsive to assertion of a conduction signal

conducting a second load current from the lower terminal to the upper terminal by:

closing the lower-main FET;

closing the upper-main FET;

driving a second turn-on current to a lower base of the transistor from a lower current source; and then

providing a second steady-state current to the lower base from the lower current source, the second steady-state current lower than the second turn-on current.

4 . The method of claim 3 wherein the first steady-state current is equal to the second steady-state current.

5 . The method claim 3 :

wherein driving the second turn-on current from the lower current source comprises driving the second turn-on current from a lower power converter based on a first lower feedback derived from an output voltage of the lower power converter; and

wherein providing the second steady-state current from the lower current source comprises providing the second steady-state current from the lower power converter based on a second lower feedback derived from current provided by the lower power converter.

6 . The method of claim 3 further comprising extracting energy for the first turn-on current and the first steady-state current from the upper terminal, and extracting energy for the second turn-on current and the second steady-state current from the upper terminal.

7 . The method claim 1 :

wherein driving the first turn-on current from the upper current source comprises driving the first turn-on current from an upper power converter based on a first setpoint; and

wherein providing the first steady-state current from the upper current source comprises driving the first steady-state current from the upper power converter based on a second setpoint different than the first setpoint.

8 . The method of claim 1 further comprising extracting energy for the first turn-on current and the first steady-state current from the upper terminal.

9 . A switch assembly comprising:

an upper terminal, and a lower terminal;

a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter;

an upper current source having a sink input coupled to the upper terminal and a source output;

an upper-main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate;

a lower-main FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; and

a controller coupled to the gate of the upper-main FET and the gate of the lower-main FET, and for a first applied voltage across the upper terminal and lower terminal, the controller configured to:

assert the gate of the upper-main FET;

assert the gate of the lower-main FET;

configure the upper current source to provide a first turn-on current to the upper base of the transistor by driving the first turn-on current from an upper power converter based on a first upper feedback derived from an output voltage of the upper power converter, and then to provide a first steady-state current to the upper base by providing the first steady-state current from the upper power converter based on a second upper feedback derived from current provided by the upper power converter, the first steady-state current lower than the first turn-on current.

10 . The switch assembly of claim 9 further comprising:

an upper-base FET defining a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate;

wherein the controller is coupled to the gate of the upper-base FET, and when the controller configures the upper current source, the controller is configured to assert the gate of the upper-base FET to couple the source output to the upper base.

11 . The switch assembly of claim 9 further comprising:

a lower current source having a sink input coupled to the lower terminal and a source output;

wherein, for a second applied voltage across the upper terminal and lower terminal, the second applied voltage of opposite polarity from the first applied voltage, the controller configured to:

assert the gate of the lower-main FET;

assert the gate of the upper-main FET; and

configure the lower current source to provide a second turn-on current to the lower base of the transistor by driving the second turn-on current from a lower power converter based on a first lower feedback derived from an output voltage of the lower power converter, and then to provide a second steady-state current to the lower base by providing the second steady-state current from the lower power converter based on a second lower feedback derived from current provided by the lower power converter, the second steady-state current lower than the second turn-on current.

12 . The switch assembly of claim 11 wherein the upper current source is a switching power converter designed and constructed to control output current as a controlled variable during at least the providing of the first steady-state current.

13 . The switch assembly of claim 11 wherein the upper current source is a switching power converter designed and constructed to control output current as a controlled variable during the providing of the first turn-on current and during the providing of the first steady-state current.

14 . The switch assembly of claim 11 further comprising:

an upper-base FET defining a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate; and

a lower-base FET defining a first lead coupled to the source output of the lower current source, a second lead coupled to the lower base, and a gate, wherein

the controller is coupled to the gate of the upper-base FET and the gate of the lower-base FET,

when the controller configures the upper current source, the controller is configured to assert the gate of the upper-base FET to couple the source output of the upper current source to the upper base, and

when the controller configures the lower current source, the controller is configured to assert the gate of the lower-base FET to couple the source output of the lower current source to the lower base.