Electronic circuit
An object of the invention is to reduce reflux of an operating current of an electronic circuit provided with a plurality of transistor circuits. The electronic circuit includes a first power supply line, a second power supply line, a third power supply line, a first transistor circuit, and a second transistor circuit. A positive power supply voltage is applied to the first power supply line. A negative power supply voltage is applied to the second power supply line. An intermediate voltage between the positive power supply voltage and the negative power supply voltage is applied to the third power supply line. The first transistor circuit is connected between the first power supply line and the third power supply line. The second transistor circuit is connected between the second power supply line and the third power supply line.
1 . An electronic circuit, comprising:
a first power supply line configured to receive a positive power supply voltage;
a second power supply line configured to receive a negative power supply voltage;
a third power supply line configured to receive an intermediate voltage, wherein the intermediate voltage is between the positive power supply voltage and the negative power supply voltage;
a first transistor circuit connected between the first power supply line and the third power supply line; and
a second transistor circuit connected between the second power supply line and the third power supply line, wherein an operation of the first transistor circuit is in synchronization with an operation of the second transistor circuit.
2 . The electronic circuit according to claim 1 , wherein
the first transistor circuit includes a first parasitic capacitance,
the first parasitic capacitance is between the first transistor circuit and the third power supply line,
the second transistor circuit includes a second parasitic capacitance, and
the second parasitic capacitance is between the second transistor circuit and the third power supply line.
3 . The electronic circuit according to claim 1 , wherein
the first power supply line is a current supply source of the first transistor circuit,
the second power supply line is a current discharge source of the second transistor circuit, and
the third power supply line is each of a current discharge source of the first transistor circuit and a current supply source of the second transistor circuit.
4 . The electronic circuit according to claim 1 , wherein the intermediate voltage is a ground voltage.
5 . The electronic circuit according to claim 1 , further comprising:
a P-type semiconductor substrate;
a first N-well in the P-type semiconductor substrate, wherein the first N-well is connected to the first power supply line;
a second N-well in the P-type semiconductor substrate, wherein the second N-well is connected to the third power supply line;
a third N-well in the first N-well, wherein the third N-well is connected to the first power supply line;
a first P-well in the first N-well, wherein the first P-well is connected to the third power supply line;
a fourth N-well in the second N-well, wherein the fourth N-well is connected to the third power supply line; and
a second P-well in the second N-well, wherein
the second P-well is connected to the second power supply line,
the first transistor circuit includes:
a first P-channel field effect transistor in the third N-well; and
a first N-channel field effect transistor in the first P-well, and
the second transistor circuit includes:
a second P-channel field effect transistor in the fourth N-well; and
a second N-channel field effect transistor in the second P-well.
6 . The electronic circuit according to claim 5 , wherein the intermediate voltage is greater than a substrate voltage of the P-type semiconductor substrate.
7 . The electronic circuit according to claim 1 , wherein each of the first transistor circuit and the second transistor circuit is a buffer.
8 . The electronic circuit according to claim 7 , wherein the buffer is a multi-stage buffer.
9 . The electronic circuit according to claim 1 , wherein
each of the first transistor circuit and the second transistor circuit includes a digital circuit and an analog circuit, and
the electronic circuit further comprises a power plane,
the power plane is associated with each of
the digital circuit,
the analog circuit, and
an application of the intermediate voltage.
10 . The electronic circuit according to claim 1 , further comprising a delay circuit configured to generate a plurality of synchronization clocks such that an operation timing of the first transistor circuit is equal to an operation timing of the second transistor circuit.
11 . The electronic circuit according to claim 1 , further comprising a level shifter configured to shift a level of a signal that is between the first transistor circuit and the second transistor circuit.
12 . The electronic circuit according to claim 1 , further comprising a regulator configured to generate the negative power supply voltage based on the positive power supply voltage.
13 . The electronic circuit according to claim 1 , further comprising:
a substrate that includes a power plane, wherein
the power plane is configured to receive the intermediate voltage, and
the power plane includes an insulating film;
a fourth power supply line configured to receive the positive power supply voltage; and
a fifth power supply line configured to receive the negative power supply voltage, wherein
each of the fourth power supply line and the fifth power supply line is on the power plane,
the fourth power supply line is adjacent to the fifth power supply line, and
the insulating film is between the fourth power supply line and fifth power supply line.