Self-synchronized scheme for enforcing phase coherency in a system with multiple frequency dividers
A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers includes synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases including a common phase. The global reset is applied to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase.
1 . A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers comprising:
synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases comprising a common phase;
applying the global reset to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase; and
reducing a metastable condition of the global reset during synchronizing the asynchronous reset by regenerating the asynchronous reset with at least one regenerative latch.
2 . The method of claim 1 further comprising controlling the VCO with a Phase-Locked Loop (PLL) controlled by the first output.
3 . The method of claim 1 further comprising applying the global reset to at least one additional divider to temporally align the first output during the common phase with a respective output of the at least one additional divider, wherein the at least one additional driver is configured to divide the VCO output to generate the respective output and applying the global reset enables respective state transitions on the respective output during the common phase.
4 . The method of claim 1 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of manufacturing processing conditions of the self-synchronizing system.
5 . The method of claim 1 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of operating voltage conditions of the self-synchronizing system.
6 . The method of claim 1 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of operating temperature conditions of the self-synchronizing system.
7 . The method of claim 1 wherein a timing of the global reset is adjusted by modifying at least one device characteristic of at least one of the second divider and the third divider.
8 . A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers comprising:
synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases comprising a common phase; and
applying the global reset to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase,
wherein applying the global reset enables respective state transitions by deactivating a respective voltage clamp on the second output and the third output.
9 . The method of claim 8 further comprising controlling the VCO with a Phase-Locked Loop (PLL) controlled by the first output.
10 . The method of claim 8 further comprising applying the global reset to at least one additional divider to temporally align the first output during the common phase with a respective output of the at least one additional divider, wherein the at least one additional driver is configured to divide the VCO output to generate the respective output and applying the global reset enables respective state transitions on the respective output during the common phase.
11 . The method of claim 8 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of manufacturing processing conditions of the self-synchronizing system.
12 . The method of claim 8 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of operating voltage conditions of the self-synchronizing system.
13 . The method of claim 8 further comprising adjusting a timing of the global reset to enable the respective state transitions during the common phase within a range of operating temperature conditions of the self-synchronizing system.
14 . The method of claim 8 wherein a timing of the global reset is adjusted by modifying at least one device characteristic of at least one of the second divider and the third divider.
15 . An apparatus comprising:
a Voltage Controlled Oscillator (VCO);
a first divider electrically coupled to the VCO and configured to generate a first output comprising a first state transition by dividing a VCO output of the VCO, the VCO output comprising a plurality of phases comprising a common phase;
a synchronizer configured to synchronize an asynchronous reset to the first output to generate a global reset, a second divider electrically coupled to the VCO and configured to generate a second output comprising a second state transition during the common phase in response to the global reset;
a third divider electrically coupled to the VCO and configured to generate a third output comprising a third state transition during the common phase in response to the global reset; and
a regenerative circuit connected between the asynchronous reset and the global reset to reduce a metastable condition of the global reset during synchronizing of the asynchronous reset with the first output.
16 . The apparatus of claim 15 wherein the regenerative circuit comprises a plurality of True Single-Phase Clock (TSPC) latches between the asynchronous reset and the global reset, and a respective pair of cross-coupled inverters between each TSPC latch, wherein the first output is configured to clock each of the TSPC latches.
17 . The apparatus of claim 15 wherein the second divider and the third divider comprise dissimilar device architectures.
18 . The apparatus of claim 15 wherein a device characteristic determining a transition time of the global reset within the common phase is different between the second divider and the third divider, to cause the global reset to transition states within a respective range of manufacturing processing conditions, operating voltage conditions and operating temperature conditions of the apparatus.
19 . An apparatus comprising:
a Voltage Controlled Oscillator (VCO);
a first divider electrically coupled to the VCO and configured to generate a first output comprising a first state transition by dividing a VCO output of the VCO, the VCO output comprising a plurality of phases comprising a common phase;
a synchronizer configured to synchronize an asynchronous reset to the first output to generate a global reset, a second divider electrically coupled to the VCO and configured to generate a second output comprising a second state transition during the common phase in response to the global reset; and
a third divider electrically coupled to the VCO and configured to generate a third output comprising a third state transition during the common phase in response to the global reset
wherein the global reset is connected to a respective voltage clamp of the second divider and the third divider, wherein each respective voltage clamp is configured to enable a respective state transition on the second output and the third output beginning during the common phase.
20 . The apparatus of claim 19 wherein the second divider and the third divider comprise dissimilar device architectures.
21 . The apparatus of claim 19 wherein a device characteristic determining a transition time of the global reset within the common phase is different between the second divider and the third divider, to cause the global reset to transition states within a respective range of manufacturing processing conditions, operating voltage conditions and operating temperature conditions of the apparatus.