Signal converter with delay architecture for concurrent signal processing
Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.
1 . An analog-to-digital converter comprising:
a pipelined successive approximation register (SAR) time-to-digital converters (TDC) device, comprising:
a plurality of SAR TDC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages,
wherein the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages; and
a delay difference generation device comprising:
a tunable delay cell having a delay based on an input digital code and modifiable in response to tuning one or more of a pull-up strength and a pull-down strength of an inverter by a switch.
2 . The device of claim 1 , the SAR TDC stage comprising:
a comparator to compare an input time-domain signal and generate a comparison output result; and
wherein the delay difference generation device can tune the delay of a top delay path and a bottom delay path according to the comparison output result.
3 . The device of claim 1 , the SAR TDC stage configured to convert the input signal into one or a plurality of digital bits.
4 . The device of claim 1 , wherein one or more of the plurality of SAR stages have a radix equal to or less than 2, the plurality of SAR stages configured to convert the input time signal to digital code successively in accordance with a cascade configuration.
5 . The device of claim 1 , the SAR TDC stage comprising:
a comparator configured to perform a time-domain signal comparison; and
a delay cell configured to generate a delay based on a time difference between two input signal to the SAR TDC.
6 . The device of claim 1 , further comprising:
one or more inverters coupled with the tunable delay cell and having a tunable pull-down strength.
7 . The device of claim 1 , one or more of the inverters arranged in one or more series paths each having a corresponding tunable delay.
8 . The device of claim 1 , further comprising:
a ramp circuit configured to generate a ramped signal based on an analog input signal; and
a signal transformer configured to convert the ramped signal into a time-domain pulse.
9 . The device of claim 8 , further comprising:
a flash time-to-digital (TDC) converter configured to generate a signal based on the time-domain pulse; and
a residue time generation circuit configured to provide the generated signal to the SAR TDC device.
10 . The device of claim 1 , further comprising:
a variable delay inverter configured to modify a delayed output signal of a SAR TDC stage.
11 . A pipelined time-to-digital converters (TDC) method, the method comprising:
converting, by a plurality of time-domain conversion stages, an input time-domain signal to a corresponding bit of a digital code in accordance with a cascade configuration; and
transmitting, by a time-domain conversion stage among the plurality of time-domain conversion stages, an output time-domain signal of the time-domain conversion stage to an input of a following time-domain conversion stage among the plurality of time-domain conversion stages,
wherein each stage is controlled by a clock signal based on a delayed clock signal from a previous time-domain conversion stage among the plurality of time-domain conversion stages.
12 . The method of claim 11 , further comprising:
performing a time-domain signal comparison; and
generating a delay based on a time difference.
13 . The method of claim 6 , further comprising:
converting the input time-domain signal into one or more bits of the digital code.
14 . The method of claim 11 , further comprising:
performing a voltage-to-time conversion to generate the input time-domain signal.
15 . The method of claim 11 , further comprising:
generating a subsequent digital bit using a time domain comparison; and
tuning a subsequent time-domain signal based on the time domain comparison.
16 . A voltage-to-time converter (VTC) device, the device comprising:
a common-mode capacitor coupled with a center node of one or more voltage sampling capacitors; and
a current source coupled with the common-mode capacitor and configured to charge the common-mode capacitor.
17 . The device of claim 16 , further comprising:
the voltage sampling capacitors and the common-mode capacitor connected to one or more of a bottom plate of the device corresponding to a ground node and the center node.
18 . The device of claim 12 , further comprising:
a plurality of common-mode capacitors including the common-mode capacitor,
wherein one or more of the plurality of common-mode capacitors are connected to the center node of the voltage sampling capacitors.
19 . The device of claim 16 , further comprising:
a plurality of current sources including the current source,
wherein one or more of the plurality of current sources are configured to charge the common-mode capacitor.
20 . The device of claim 16 , wherein the common-mode capacitor is reset responsive to conversion of a voltage signal to a time-domain signal.