IP Library Granted Patent US 12665614
Granted Patent B2
US 12665614 · App. 18/647,699 · Granted Jun 23, 2026

System and method for low density parity check (LDPC) code with 5/6 code rate

Inventors: Rethnakaran Pulikkoonattu (San Diego, CA); Andrew Blanksby (Irvine, CA); Vinko Erceg (Irvine, CA)
Assignee: Avago Technologies International Sales Pte. Limited
H03M13/116H03M13/118
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Quick Facts
Patent No.
US 12665614
App. No.
18/647,699
Granted
Jun 23, 2026
Kind
B2
Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

Claims (56)

1 . A method for increasing a gain in a signal-to-noise (SNR) of a channel compared with encoding data using a quasi-cyclic-low-density parity-check (QC-LDPC) code corresponding to a code block size smaller than 3888 bits, comprising:

identifying, by baseband circuitry of a first device according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a QC-LDPC code, the first binary parity check matrix corresponding to a first exponent matrix having 96 values;

encoding, by an encoder of the baseband circuitry of the first device, data using the first binary parity check matrix; and

transmitting, by a transmitter of the first device, the encoded data over the channel.

2 . The method of claim 1 , further comprising:

generating the first exponent matrix by selecting at least 94 values from a second exponent matrix having the same dimensions as dimensions of the first exponent matrix.

3 . The method of claim 2 , further comprising:

shifting one or two values of the first exponent matrix from one or more corresponding positive values of the second exponent matrix by −1 or +1,

wherein the one or more corresponding positive values of the second exponent matrix are not selected as the at least 94 values.

4 . The method of claim 2 , wherein the second exponent matrix comprises the following set of values:

[28 96 161 134 9 149 15 61 153 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 127 148 114 128 156 114 130 14 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 104 32 1 160 49 52 85 108 90 144 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 114 119 75 101 49 −1 131 8 131 105 −1 9 −1 146 105 2 −1 −1 0].

5 . The method of claim 2 , wherein the second exponent matrix comprises the following set of values:

[27 96 160 133 9 148 15 60 152 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 126 148 113 128 155 114 130 13 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 103 31 1 160 48 51 84 108 89 143 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 113 119 75 100 49 −1 131 8 131 105 −19 −1 146 105 2 −1 −1 0].

6 . The method of claim 1 , further comprising:

identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as dimensions of the first binary parity check matrix; and

encoding, by the encoder, data using the second binary parity check matrix.

7 . The method of claim 1 , further comprising:

identifying a third binary parity check matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as dimensions of the first exponent matrix; and

encoding, by the encoder, data using the third binary parity check matrix.

8 . The method of claim 1 , further comprising:

generating the first binary parity check matrix using (1) a matrix product of the first binary parity check matrix and the first exponent matrix, or (2) a matrix product of the first exponent matrix and the first binary parity check matrix.

9 . The method of claim 1 , further comprising:

identifying, by a second device, the first binary parity check matrix;

receiving, by the second device from the first device, the encoded data; and

decoding, by the second device, the encoded data using the first binary parity check matrix.

10 . An apparatus for increasing a gain in a signal-to-noise (SNR) of a channel compared with encoding data using a quasi-cyclic-low-density parity-check (QC-LDPC) code corresponding to a code block size smaller than 3888 bits, the apparatus comprising:

a transmitter and baseband circuitry, wherein the baseband circuitry is configured to:

identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a QC-LDPC code, the first binary parity check matrix corresponding to a first exponent matrix having 96 values;

encode, by an encoder of the baseband circuitry, data using the first binary parity check matrix; and

transmit, by the transmitter, the encoded data over the channel.

11 . The apparatus of claim 10 , wherein the baseband circuitry further configured to:

generate the first exponent matrix by selecting at least 94 values from a second exponent matrix having the same dimensions as dimensions of the first exponent matrix.

12 . The apparatus of claim 11 , wherein the baseband circuitry is further configured to:

shift one or two values of the first exponent matrix from one or more corresponding positive values of the second exponent matrix by −1 or +1,

wherein the one or more corresponding positive values of the second exponent matrix are not selected as the at least 94 values.

13 . The apparatus of claim 11 , wherein the second exponent matrix comprises the following set of values:

[28 96 161 134 9 149 15 61 153 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 127 148 114 128 156 114 130 14 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 104 32 1 160 49 52 85 108 90 144 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 114 119 75 101 49 −1 131 8 131 105 −1 9 −1 146 105 2 −1 −1 0].

14 . The apparatus of claim 11 , wherein the second exponent matrix comprises the following set of values:

[27 96 160 133 9 148 15 60 152 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 126 148 113 128 155 114 130 13 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 103 31 1 160 48 51 84 108 89 143 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 113 119 75 100 49 −1 131 8 131 105 −19 −1 146 105 2 −1 −1 0].

15 . The apparatus of claim 10 , wherein the baseband circuitry is further configured to:

identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as dimensions of the first binary parity check matrix; and

encode data using the second binary parity check matrix.

16 . The apparatus of claim 10 , wherein the baseband circuitry is further configured to:

identify a third binary parity check matrix corresponding to a second exponent matrix in which one or more columns of the first exponent matrix are permuted, the second exponent matrix having the same dimensions as dimensions of the first exponent matrix; and

encode data using the third binary parity check matrix.

17 . The apparatus of claim 10 , wherein the baseband circuitry is further configured to:

generate the first binary parity check matrix using (1) a matrix product of the first binary parity check matrix and the first exponent matrix, or (2) a matrix product of the first exponent matrix and the first binary parity check matrix.

18 . An apparatus for increasing a gain in a signal-to-noise (SNR) of the channel compared with encoding data using a quasi-cyclic-low-density parity-check (QC-LDPC) code corresponding to a code block size smaller than 3888 bits, the apparatus comprising:

a receiver configured to receive encoded data over the channel, wherein the encoded data is encoded using a first binary parity check matrix for a QC-LDPC code according to a code rate of 5/6 and a code block size of 3888 bits; and

baseband circuitry configured to:

identify, according to the code rate of 5/6 and the code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponent matrix having 96 values; and

decode the received encoded data using the first binary parity check matrix.

19 . The apparatus of claim 18 , wherein the first exponent matrix comprises the following set of values:

[28 96 161 134 9 149 15 61 153 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 127 148 114 128 156 114 130 14 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 104 32 1 160 49 52 85 108 90 144 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 114 119 75 101 49 −1 131 8 131 105 −1 9 −1 146 105 2 −1 −1 0].

20 . The apparatus of claim 18 , wherein the first exponent matrix comprises the following set of values:

[27 96 160 133 9 148 15 60 152 105 75 120 −1 98 146 63 149 147 46 −1 2 0 −1 −1 138 126 148 113 128 155 114 130 13 33 103 −1 128 −1 136 18 96 124 109 55 −1 0 0 −1 103 31 1 160 48 51 84 108 89 143 143 18 134 70 −1 117 −1 59 −1 107 0 −1 0 0 33 58 73 83 89 113 119 75 100 49 −1 131 8 131 105 −19 −1 146 105 2 −1 −1 0].