Techniques for reducing filter distortion in data using emphasis
An integrated circuit includes a filter circuit and a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit. The emphasis is determined based on the distortion caused by the filter circuit. A circuit design system includes logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, use the relaxed parameters to generate a second filter circuit that filters data, generate an emphasis vector based on distortion in the data caused by the second filter circuit, and generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.
1 . An integrated circuit comprising:
a filter circuit; and
a computation circuit that applies emphasis to a data stream in a frequency domain to reduce distortion to the data stream caused by the filter circuit, wherein the emphasis is determined based on the distortion caused by the filter circuit, wherein the filter circuit and the computation circuit are part of a transmitter circuit, and wherein the emphasis comprises a pre-emphasis vector.
2 . The integrated circuit of claim 1 , wherein the emphasis comprises an inverse of the distortion caused by the filter circuit.
3 . The integrated circuit of claim 1 , wherein the computation circuit comprises a multiplier circuit that multiplies the emphasis with data in the data stream in the frequency domain.
4 . The integrated circuit of claim 1 , wherein first values that are products of second values of the pre-emphasis vector and twiddle factors are multiplied with data in the data stream during an inverse Fourier transform performed by the computation circuit to generate an output data signal.
5 . The integrated circuit of claim 4 , wherein the first values are computed prior to the computation circuit applying the emphasis to the data stream, and wherein the first values are stored in a memory circuit.
6 . The integrated circuit of claim 4 , wherein the filter circuit filters the output data signal generated by the computation circuit.
7 . The integrated circuit of claim 1 , wherein the computation circuit performs an inverse fast Fourier transform on the data stream, and an output signal of the computation circuit is provided to an input of the filter circuit.
8 . The integrated circuit of claim 1 further comprising:
a multiplier circuit that multiplies data in the data stream by the pre-emphasis vector in the frequency domain to generate a data signal.
9 . The integrated circuit of claim 8 , wherein the computation circuit performs an inverse fast Fourier transform on the data signal to generate a modulated data stream in an output signal that is provided to an input of the filter circuit.
10 . A method for reducing distortion in data caused by a filter circuit, the method comprising:
filtering the data using the filter circuit to generate filtered data; and
applying emphasis to the filtered data in a frequency domain to compensate for the distortion in the filtered data using a computation circuit by applying a post-emphasis vector to the filtered data after the filter circuit filters the data to generate the filtered data, wherein the emphasis is generated based on the distortion.
11 . The method of claim 10 , wherein the emphasis comprises an inverse of the distortion caused by the filter circuit.
12 . The method of claim 10 , wherein applying the emphasis to the filtered data further comprises multiplying the post-emphasis vector with the filtered data using a multiplier circuit.
13 . The method of claim 10 , wherein applying the emphasis to the filtered data further comprises multiplying the filtered data with first values that are products of second values of the post-emphasis vector and twiddle factors during a Fourier transform performed by the computation circuit.
14 . The method of claim 10 , wherein applying the emphasis to the filtered data further comprises performing a fast Fourier transform on the filtered data signal to generate a demodulated data stream in an output data signal.
15 . The method of claim 10 , wherein the filter circuit and the computation circuit are part of a receiver circuit.
16 . A circuit design system configured to implement a circuit design tool for generating a circuit design for an integrated circuit, wherein the circuit design system comprises:
logic synthesis and optimization tools that relax parameters for a first filter circuit to generate relaxed parameters, wherein the logic synthesis and optimization tools use the relaxed parameters to generate a second filter circuit that filters data, wherein the logic synthesis and optimization tools generate an emphasis vector based on distortion in the data caused by the second filter circuit, and
wherein the logic synthesis and optimization tools generate a computation circuit that applies the emphasis vector to the data to reduce the distortion in the data caused by the second filter circuit.
17 . The circuit design system of claim 16 , wherein the relaxed parameters comprise a number of taps, and wherein the logic synthesis and optimization tools reduce the number of taps in the second filter circuit compared to the first filter circuit.
18 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools iteratively relax the parameters by calculating a maximum value of the emphasis vector in each iteration of a set of iterations until a maximum acceptable word growth for the data is reached.
19 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools generate a multiplier circuit that multiplies the emphasis vector with the data to reduce the distortion in the data caused by the second filter circuit.
20 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools generate the computation circuit that multiplies the data with values that are products of the emphasis vector multiplied with twiddle factors of a Fourier transform performed by the computation circuit.