Apparatus and method for transition-sensing based clock recovery in burst mode time-division multiple-access communication system
A burst mode communication system may include one or more lanes. Each lane is configured to receive burst data streams sent according to a clock signal and recover the clock signal. A lane may receive a first burst data stream and a second burst data stream in two adjacent clock cycles of the clock signal, and convert the first burst data stream into a first pulse signal and convert the second burst data stream into a second pulse signal. The lane may recover the clock signal by detecting a time interval between rising edges of the first pulse signal and the second pulse signal. The burst data streams are different signals and sent to the burst mode communication system in the time-division multiple-access (TDMA) scheme. A clock recovery circuit is also provided in the lane for recovering the clock signal.
1 . A lane of a burst mode communication system, comprising:
a transceiver configured to receive burst data streams sent according to a clock signal having a clock frequency; and
a clock recovery circuit in communication with the transceiver and configured to:
receive, from the transceiver, a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal, the second clock cycle being adjacent to the first clock cycle;
convert the first burst data stream into a first pulse signal and convert the second burst data stream into a second pulse signal; and
recover the clock signal based on a time interval between rising edges of the first pulse signal and the second pulse signal;
wherein each of the burst data streams is a differential signal, which comprises a first signal being a positive component of the differential signal and a second signal being a negative component of the differential signal.
2 . The lane of claim 1 , wherein recovering the clock signal comprises determining the clock frequency based on the time interval.
3 . The lane of claim 1 , wherein the clock recovery circuit comprises:
a first amplifier circuit having a first positive input terminal and a first negative input terminal, wherein the first amplifier circuit is configured to: receive the first signal of a burst data stream of the burst data streams at the first positive input terminal, receive the second signal of the burst data stream at the first negative input terminal, and generate a first differential signal of the burst data stream;
a second amplifier circuit having a second positive input terminal and a second negative input terminal, wherein the second amplifier circuit is configured to: receive the first signal of the burst data stream at the second negative input terminal, receive the second signal of the burst data stream at the second positive input terminal, and generate a second differential signal of the burst data stream;
a first differential to single-ended conversion circuit connected to the first amplifier circuit, and configured to convert the first differential signal of the burst data stream into a first single-ended signal;
a second differential to single-ended conversion circuit connected to the second amplifier circuit, and configured to convert the second differential signal of the burst data stream into a second single-ended signal; and
a filter circuit connected to the first differential to single-ended conversion circuit and the second differential to single-ended conversion circuit, wherein the filter circuit is configured to process the first single-ended signal and the second single-ended signal to generate a pulse signal of the burst data stream.
4 . The lane of claim 3 , wherein:
the first amplifier circuit comprises:
a first switch and a second switch connected in parallel between a first node and a first current source, wherein drains of the first switch and the second switch are connected to the first node, sources of the first switch and the second switch are connected to the first current source, and gates of the first switch and the second switch are connected to the second signal of the burst data stream; and
a third switch having a gate connected to the first signal of the burst data stream, a source connected to the first current source, and a drain connected to a second node, wherein the first node and the second node are connected to the first differential to single-ended conversion circuit; and
the second amplifier circuit comprises:
a fourth switch and a fifth switch connected in parallel between a third node and a second current source, wherein drains of the fourth switch and the fifth switch are connected to the third node, sources of the fourth switch and the fifth switch are connected to the second current source, and gates of the fourth switch and the fifth switch are connected to the first signal of the burst data stream; and
a sixth switch having a gate connected to the second signal of the burst data stream, a source connected to the second current source, and a drain connected to a fourth node, wherein the third node and the fourth node are connected to the second differential to single-ended conversion circuit.
5 . The lane of claim 4 , further comprising:
a first load, a second load, a third load and a fourth load coupled to the first node, the second node, the third node and the fourth node, respectively.
6 . The lane of claim 5 , wherein the first load, the second load, the third load and the fourth load are coupled between ground and the first node, the second node, the third node and the fourth node, respectively.
7 . The lane of claim 5 , wherein the first load, the second load, the third load and the fourth load are coupled between a power supply and the first node, the second node, the third node and the fourth node, respectively.
8 . The lane of claim 4 , wherein the first switch and the fourth switch have an on-resistance less than the second switch, the third switch, the fifth switch and the sixth switch.
9 . The lane of claim 4 , wherein the first to sixth switches are field-effect transistors (FETs).
10 . The lane of claim 3 , wherein the filter circuit comprises:
a first OR gate having a first input terminal connected to the first differential to single-ended conversion circuit, and a second input terminal connected to the second differential to single-ended conversion circuit, wherein the first OR gate is configured to perform an OR operation on the first single-ended signal and the second single-ended signal to generate a first filtered signal of the burst data stream at an output terminal of the first OR gate;
a delay circuit connected to the output terminal of the first OR gate, wherein the delay circuit is configured to delay the first filtered signal to generate a delayed signal; and
a second OR gate configured to receive the delayed signal and the first filtered signal and generate the pulse signal of the burst data stream.
11 . A burst mode communication system comprising at least one lane, the at least one lane comprising;
a transceiver configured to receive burst data streams sent to the burst mode communication system according to a clock signal having a clock frequency; and
a clock recovery circuit in communication with the transceiver and configured to:
receive, from the transceiver, a first burst data stream in a first clock cycle of the clock signal and a second burst data stream in a second clock cycle of the clock signal, the second clock cycle being adjacent to the first clock cycle;
convert the first burst data stream into a first pulse signal and convert the second burst data stream into a second pulse signal; and
recover the clock signal by detecting a time difference between rising edges of the first pulse signal and the second pulse signal;
wherein each of the burst data streams is a differential signal, which comprises a first signal being a positive component of the differential signal and a second signal being a negative component of the differential signal.
12 . The burst mode communication system of claim 11 , wherein recovering the clock signal comprises determining the clock frequency based on the time difference detected.
13 . The burst mode communication system of claim 12 , wherein the clock recovery circuit comprises:
a first amplifier circuit having a first positive input terminal and a first negative input terminal, wherein the first amplifier circuit is configured to: receive the first signal of a burst data stream of the burst data streams at the first positive input terminal, receive the second signal of the burst data stream at the first negative input terminal, and generate a first differential signal of the burst data stream;
a second amplifier circuit having a second positive input terminal and a second negative input terminal, wherein the second amplifier circuit is configured to: receive the first signal of the burst data stream at the second negative input terminal, receive the second signal of the burst data stream at the second positive input terminal, and generate a second differential signal of the burst data stream;
a first differential to single-ended conversion circuit coupled to the first amplifier circuit, and configured to convert the first differential signal of the burst data stream into a first single-ended signal;
a second differential to single-ended conversion circuit coupled to the second amplifier circuit, and configured to convert the second differential signal of the burst data stream into a second single-ended signal; and
a filter circuit connected to the first differential to single-ended conversion circuit and the second differential to single-ended conversion circuit, wherein the filter circuit is configured to process the first single-ended signal and the second single-ended signal to generate a pulse signal of the burst data stream.
14 . The burst mode communication system of claim 13 , wherein:
the first amplifier circuit comprises:
a first switch and a second switch connected in parallel between a first node and a first current source, wherein drains of the first switch and the second switch are connected to the first node, sources of the first switch and the second switch are connected to the first current source, and gates of the first switch and the second switch are connected to the second signal of the burst data stream; and
a third switch having a gate connected to the first signal of the burst data stream, a source connected to the first current source, and a drain connected to a second node, wherein the first node and the second node are connected to the first differential to single-ended conversion circuit; and
the second amplifier circuit comprises:
a fourth switch and a fifth switch connected in parallel between a third node and a second current source, wherein drains of the fourth switch and the fifth switch are connected to the third node, sources of the fourth switch and the fifth switch are connected to the second current source, and gates of the fourth switch and the fifth switch are connected to the first signal of the burst data stream; and
a sixth switch having a gate connected to the second signal of the burst data stream, a source connected to the second current source, and a drain connected to a fourth node, wherein the third node and the fourth node are connected to the second differential to single-ended conversion circuit.
15 . The burst mode communication system of claim 14 , wherein the clock recovery circuit further comprises:
a first load, a second load, a third load and a fourth load coupled to the first node, the second node, the third node and the fourth node, respectively.
16 . The burst mode communication system of claim 14 , wherein the first switch and the fourth switch have an on-resistance less than the second switch, the third switch, the fifth switch and the sixth switch.
17 . The burst mode communication system of claim 14 , wherein the first to sixth switches are field-effect transistors (FETs).
18 . The burst mode communication system of claim 13 , wherein the filter circuit comprises:
a first OR gate having a first input terminal connected to the first differential to single-ended conversion circuit, and a second input terminal connected to the second differential to single-ended conversion circuit, wherein the first OR gate is configured to perform an OR operation on the first single-ended signal and the second single-ended signal to generate a first filtered signal of the burst data stream at an output terminal of the first OR gate;
a delay circuit connected to the output terminal of the first OR gate, wherein the delay circuit is configured to delay the first filtered signal to generate a delayed signal; and
a second OR gate configured to receive the delayed signal and the first filtered signal and generate the pulse signal of the burst data stream.
19 . The burst mode communication system of claim 11 , further comprising:
clock multiplier in communication with the at least one lane, and configured to:
receive the recovered clock signal; and
generate a data frequency of the burst data streams based on the recovered clock signal.
20 . The burst mode communication system of claim 19 , further comprising:
a physical coding sublayer in communication with the clock multiplier, the physical coding sublayer being configured to receive the data frequency from the clock multiplier and process one or more of the burst data streams based on the data frequency.