Processing system, related integrated circuit, device and method

1 . A processing system comprising:

a positive supply terminal and a negative supply terminal; and

a sub-circuit comprising:

a transmission terminal;

a three-state driver circuit comprising:

a first electronic switch connected between the transmission terminal and the positive supply terminal; and

a second electronic switch connected between the transmission terminal and the negative supply terminal,

wherein the three-state driver circuit comprises a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal:

in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch,

in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and

in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch; and

a CAN FD light controller configured to sequentially transmit bits of a CAN FD light frame, wherein the CAN FD light frame comprises:

a start-of-frame bit,

a sequence of bits comprising in sequence a Cyclic Redundancy Check (CRC), delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and

a plurality of intermediate bits between the start-of-frame bit and the CRC delimiter bit, and

wherein the CAN FD light controller is configured to sequentially transmit, in a first operating mode, the bits of the CAN FD light frame by generating the first signal and the second signal in response to a transmission clock signal in order to:

transmit the start-of-frame bit by activating the second switching state for one clock cycle,

sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating the first or second switching states as a function of the logic level of the selected bit, and

once having transmitted the intermediate bits, activate the third switching state.

2 . The processing system according to claim 1 , wherein the CAN FD light controller is configured to transmit the sequence of bits by activating the third switching state for 10 clock cycles.

3 . The processing system according to claim 1 , wherein the combinational logic circuit of the three-state driver circuit is configured to:

in response to determining that the first signal is de-asserted, activate the second switching state,

in response to determining that the first signal is asserted and the second signal is asserted, activate the first switching state, and

in response to determining that the first signal is asserted and the second signal is de-asserted, activate the third switching state.

4 . The processing system according to claim 3 , wherein the CAN FD light controller is configured to:

generate a transmission signal by sequentially providing the bits of the CAN FD light frame in response to the transmission clock signal as the first signal;

assert the second signal when providing the start-of-frame bit and the intermediate bits; and

de-assert the second signal when providing the sequence of bits.

5 . The processing system according to claim 4 , wherein the CAN FD light controller comprises:

a digital processing circuit configured to generate a frame comprising at least the intermediate bits of the CAN FD light frame;

a serial communication interface comprising a control register configured to store data identifying a requested number of bits;

a clock management circuit configured to receive a system clock signal and generate a down-scaled clock signal, wherein the transmission clock signal corresponds to the down-scaled clock signal;

a transmission shift register configured to generate the transmission signal, when a transmission enable signal is asserted, by sequentially providing a content of the transmission shift register in response to the transmission clock signal, wherein the processing system is configured to selectively transfer the frame from the digital processing circuit to the transmission shift register; and

a transmission control circuit configured to:

receive a start of transmission signal requesting transmission of data,

in response to the start of transmission signal, assert the transmission enable signal,

when the transmission enable signal is asserted, increase a transmission count value in response to the transmission clock signal,

determine whether the transmission count value reaches the requested number of bits, and

in response to determining that the transmission count value reaches the requested number of bits, de-assert the transmission enable signal.

6 . The processing system according to claim 5 , wherein the transmission control circuit is configured to:

in response to the start of transmission signal, assert the second signal,

determine whether the serial communication interface provides the last bit of the intermediate bits, and

in response to determining that the transmission shift register provides the last bit of the intermediate bits, de-assert the second signal.

7 . The processing system according to claim 1 , wherein the combinational logic circuit of the three-state driver circuit is configured to:

in response to determining that the first signal is de-asserted and the second signal is asserted, activate the second switching state,

in response to determining that the first signal is asserted and the second signal is asserted, activate the first switching state, and

in response to determining that the second signal is de-asserted, activate the third switching state.

8 . The processing system according to claim 1 , further comprising:

a CAN FD transceiver comprising a transmission terminal and a reception terminal,

wherein the transmission terminal of the CAN FD transceiver is connected to the transmission terminal of the sub-circuit and the reception terminal of the CAN FD transceiver is connected to the reception terminal of the sub-circuit, and

wherein, in a second operating mode, the CAN FD light controller is configured to sequentially transmit the bits of the CAN FD light frame by generating the first signal and the second signal in response to a transmission clock signal in order to:

transmit the start-of-frame bit by activating the second switching state for one clock cycle,

sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating the first or the second switching state as a function of the logic level of the selected bit, and

once having transmitted the intermediate bits, activate the first switching state.

9 . An integrated circuit comprising:

the processing system according to claim 1 .

10 . A method for operating the processing system according to claim 1 , the method comprising:

sequentially transmitting the bits of the CAN FD light frame.

11 . A processing system comprising:

a positive supply terminal and a negative supply terminal; and

a sub-circuit comprising:

a transmission terminal;

a three-state driver circuit comprising:

a first electronic switch connected between the transmission terminal and the positive supply terminal; and

a second electronic switch connected between the transmission terminal and the negative supply terminal,

wherein the three-state driver circuit comprises a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal:

in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch,

in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and

in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch;

a CAN FD light controller configured to sequentially transmit bits of a CAN FD light frame, wherein the CAN FD light frame comprises:

a start-of-frame bit,

a sequence of bits comprising in sequence a Cyclic Redundancy Check (CRC), delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and

a plurality of intermediate bits between the start-of-frame bit and the CRC delimiter bit, and

wherein the CAN FD light controller is configured to sequentially transmit, in a first operating mode, the bits of the CAN FD light frame by generating the first signal and the second signal in response to a transmission clock signal in order to:

transmit the start-of-frame bit by activating the second switching state for one clock cycle,

sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating the first or second switching states as a function of the logic level of the selected bit, and

once having transmitted the intermediate bits, activate the third switching state; and

a reception terminal, wherein the CAN FD light controller is configured to sequentially receive the bits of a further CAN FD light frame via the reception terminal.

12 . The processing system according to claim 11 , further comprising a CAN FD transceiver comprising a transmission terminal and a reception terminal, wherein the transmission terminal of the CAN FD transceiver is connected to the transmission terminal of the sub-circuit, and wherein the reception terminal of the CAN FD transceiver is connected to the reception terminal of the sub-circuit.

13 . The processing system according to claim 11 , further comprising a further sub-circuit including a further transmission terminal, a further reception terminal, a further three-state driver circuit and a further CAN FD light controller, wherein the further transmission terminal of the further sub-circuit is connected to the transmission terminal of the sub-circuit, wherein the reception terminal of the further sub-circuit is connected to the transmission terminal of the further sub-circuit, and wherein the reception terminal of the sub-circuit is connected to the transmission terminal of the sub-circuit.

14 . The processing system according to claim 12 , further comprising a further sub-circuit including a further transmission terminal, a further reception terminal, a further three-state driver circuit and a further CAN FD light controller, wherein the further transmission terminal of the further sub-circuit is connected to the transmission terminal of the sub-circuit and the reception terminal of the further sub-circuit is connected to the reception terminal of the sub-circuit.

15 . The processing system according to claim 14 , further comprising a pull-up resistance connected between the transmission terminal of the sub-circuit and the positive supply terminal.

16 . A vehicle comprising:

a plurality of processing systems, each processing system according to claim 10 , wherein the CAN FD transceivers of the processing systems are connected to a CAN bus.

17 . The processing system according to claim 16 , further comprising a pull-up resistance connected between the transmission terminal of the sub-circuit and the positive supply terminal.

18 . A method for operating a processing system comprising:

sequentially transmitting bits of a CAN FD light frame in a commander/responder communication protocol, the commander/responder communication protocol comprising a CAN FD Light protocol, wherein the CAN FD light frame comprises:

a start-of-frame bit,

a sequence of bits comprising in sequence a Cyclic Redundancy Check (CRC) delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and

a plurality of intermediate bits between the start-of-frame bit and the CRC delimiter bit,

wherein transmitting the bits of the CAN FD light frame comprises generating a first signal and a second signal of the processing system in response to a transmission clock signal in order to:

transmit the start-of-frame bit by activating a second switching state for one clock cycle,

sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating a first switching state or the second switching state as a function of a logic level of a selected bit, and

once having transmitted the intermediate bits, activate a third switching state, wherein generating the first signal and the second signal comprises:

controlling a three-state driver circuit comprising:

a first electronic switch connected between a transmission terminal and a positive supply terminal,

a second electronic switch connected between the transmission terminal and a negative supply terminal, and

a combinational logic circuit configured to monitor logic levels of the first signal and the second signal and selectively activate the first switching state by closing the first electronic switch, the second switching state by closing the second electronic switch, and the third switching state by opening both the first electronic switch and the second electronic switch.

19 . The method of claim 18 , wherein:

activating the first switching state and the second switching state comprises using a push-pull configuration to actively drive the transmission terminal, and

activating the third switching state comprises placing the transmission terminal in a high-impedance state to enable passive transmission of the acknowledge bit, the acknowledge delimiter bit, and the End-of-Frame field.

20 . The method of claim 18 , wherein the sequence of bits is transmitted by activating the third switching state for 10 clock cycles.