Equalization for pulse-amplitude modulation
Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.
1 . An apparatus comprising:
a host device configured to be coupled to an interconnect, the host device further configured to:
transmit, to a memory device, test data using a signal with a pulse amplitude modulation (PAM) having at least four levels;
transmit, to the memory device, a request to read the test data;
receive data from the memory device responsive to the transmission of the request to read the test data;
adjust one or more of various parameters to reduce an error associated with the test data;
determine a command to configure decision-feedback equalization at the memory device responsive to the reduced error associated with the test data; and
transmit, to the memory device, the command to cause the memory device to selectively engage the decision-feedback equalization.
2 . The apparatus of claim 1 , wherein the host device is further configured to:
determine the command to cause the memory device to apply the decision-feedback equalization to at least one slicer path of multiple slicer paths of the memory device.
3 . The apparatus of claim 2 , wherein the host device is further configured to:
determine the command to direct the memory device to apply the decision-feedback equalization to a proper subset of a total set of the multiple slicer paths using at least one switch of the memory device.
4 . The apparatus of claim 1 , wherein the host device is further configured to:
encode the test data carried by the signal to cause an eye height of the signal to be less than another eye height of the signal.
5 . The apparatus of claim 1 , wherein the command is configured to adjust at least one of a termination impedance or a slicer threshold at the memory device.
6 . The apparatus of claim 1 , wherein the command is configured to cause the memory device to couple a decision-feedback equalizer circuit to a digital data line of multiple digital data lines of the memory device, the command indicative of the digital data line.
7 . The apparatus of claim 1 , wherein:
the host device comprises a memory controller;
the host device is configured to be coupled to the interconnect via the memory controller; and
the memory controller is configured to perform the transmission of the test data, the transmission of the request to read the test data, the reception of the data from the memory device, the adjustment of the one or more of various parameters, the determination of the command, and the transmission of the command.
8 . An apparatus comprising:
a memory controller configured to be coupled to an interconnect, the memory controller further configured to:
transmit, to a memory device, test data using a signal with a pulse amplitude modulation (PAM) having at least four levels;
transmit, to the memory device, a request to read the test data;
receive data from the memory device responsive to the transmission of the request to read the test data;
adjust one or more of various parameters to reduce an error associated with the test data;
determine a command to configure decision-feedback equalization at the memory device responsive to the reduced error associated with the test data; and
transmit, to the memory device, the command to cause the memory device to selectively engage the decision-feedback equalization.
9 . The apparatus of claim 8 , wherein the memory controller is further configured to:
determine the command to cause the memory device to apply the decision-feedback equalization to at least one slicer path of multiple slicer paths of the memory device.
10 . The apparatus of claim 9 , wherein the memory controller is further configured to:
determine the command to direct the memory device to apply the decision-feedback equalization to a proper subset of a total set of the multiple slicer paths using at least one switch of the memory device.
11 . The apparatus of claim 8 , wherein the memory controller is further configured to:
encode the test data carried by the signal to cause an eye height of the signal to be less than another eye height of the signal.
12 . The apparatus of claim 8 , wherein the command is configured to adjust at least one of a termination impedance or a slicer threshold at the memory device.
13 . The apparatus of claim 8 , wherein the command is configured to cause the memory device to couple a decision-feedback equalizer circuit to a digital data line of multiple digital data lines of the memory device, the command indicative of the digital data line.
14 . An apparatus comprising:
an interconnect;
a memory device coupled to the interconnect;
a host device coupled to the interconnect, the host device configured to:
transmit, to the memory device, test data using a signal with a pulse amplitude modulation (PAM) having at least four levels;
transmit, to the memory device, a request to read the test data;
receive data from the memory device responsive to the transmission of the request to read the test data;
adjust one or more of various parameters to reduce an error associated with the test data;
determine a command to configure decision-feedback equalization at the memory device responsive to the reduced error associated with the test data; and
transmit, to the memory device, the command to cause the memory device to selectively engage the decision-feedback equalization, the memory device comprising control circuitry configured to:
receive, from the host device, the test data according to the signal propagated using the PAM having at least four levels;
split the signal into multiple split signals;
slice the multiple split signals to produce multiple digital signals;
apply the decision-feedback equalization to a portion of the multiple digital signals;
decode the test data:
based on the application of the decision-feedback equalization, and
using at least the portion of the multiple digital signals and at least one digital signal of the multiple digital signals that is separate from the portion to which the decision-feedback equalization is applied;
transmit, to the host device, the data, which is based on the decoded test data, responsive to the request to read the test data; and
receive, from the host device, the command to cause the memory device to selectively engage the decision-feedback equalization based on the transmission of the data, which is based on the decoded test data.
15 . The apparatus of claim 14 , wherein:
the control circuitry comprises:
a decision-feedback equalizer circuit; and
at least one switch coupled to the decision-feedback equalizer circuit; and
the control circuitry is further configured to close the at least one switch based on the command to engage the decision-feedback equalizer circuit.
16 . The apparatus of claim 15 , wherein:
the control circuitry further comprises multiple digital data lines; and
the at least one switch is configured to selectively couple the decision-feedback equalizer circuit to different ones of the multiple digital data lines that are respectively associated with different digital signals of the multiple digital signals.
17 . The apparatus of claim 14 , wherein:
the control circuitry comprises:
a decision-feedback equalizer circuit; and
at least one switch coupled to the decision-feedback equalizer circuit; and
the control circuitry is further configured to:
receive other data from the host device;
bypass the decision-feedback equalizer circuit based on the command; and
decode the other data based on the decision-feedback equalizer circuit being bypassed.
18 . The apparatus of claim 14 , wherein:
the control circuitry comprises at least one comparator that corresponds to at least one reference voltage level, the at least one comparator associated with a subset of the multiple split signals, the subset being less than a quantity of the multiple split signals; and
the control circuitry is further configured to adjust the at least one reference voltage level according to the command.
19 . The apparatus of claim 18 , wherein the control circuitry is further configured to:
receive other data from the host device according to a second signal;
split the second signal into multiple second split signals;
slice the multiple second split signals to produce multiple second digital signals based on the adjustment of the at least one reference voltage level according to the command;
equalize a subset of the multiple second digital signals, the subset being less than a quantity of the multiple second digital signals; and
decode the other data based on the equalization of the subset of the multiple second digital signals.
20 . The apparatus of claim 14 , wherein:
the command is associated with at least one impedance corresponding to an input data line for the memory device; and
the control circuitry is further configured to adjust the at least one impedance according to the command.