IP Library Granted Patent US 12665846
Granted Patent B2
US 12665846 · App. 18/342,778 · Granted Jun 23, 2026

Manageability data handling for heterogeneous computing platforms

Inventors: Adolfo S. Montero (Pflugerville, TX); Abeye Teshome (Austin, TX); Alok Pant (Austin, TX)
Assignee: Dell Products L.P.
H04L45/74H04L45/44H04L69/22
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Quick Facts
Patent No.
US 12665846
App. No.
18/342,778
Granted
Jun 23, 2026
Kind
B2
Abstract

Systems and methods for manageability data handling for heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include: a heterogeneous computing platform and an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into or coupled to the heterogeneous computing platform, where the OOB MCU is configured to receive, from a cloud service, a packet stored in a command buffer associated with the IHS, and where the packet comprises at least one of: a baseline packet, or an opaque packet.

Claims (27)

1 . An Information Handling System (IHS), comprising:

a heterogeneous computing platform; and

an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into or coupled to the heterogeneous computing platform, wherein the OOB MCU is configured to receive, from a cloud service, a packet stored in a command buffer associated with the IHS, and wherein the packet comprises at least one of: a baseline packet, or an opaque packet;

wherein the baseline packet is assembled using a map, key, or decode ring known to a manufacturer of the heterogeneous computing platform.

2 . The IHS of claim 1 , wherein the heterogeneous computing platform comprises: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC).

3 . The IHS of claim 1 , wherein the heterogeneous computing platform comprises a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect.

4 . The IHS of claim 3 , wherein the plurality of devices comprises at least one of:

a Graphical Processing Unit (GPU), an audio Digital Signal Processor (aDSP), a sensor hub, a Neural Processing Unit (NPU), a Tensor Processing Unit (TSU), a Neural Network Processor (NNP), an Intelligence Processing Unit (IPU), an Image Signal Processor (ISP), or a Video Processing Unit (VPU).

5 . The IHS of claim 3 , wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus.

6 . The IHS of claim 1 , wherein the OOB MCU is configured to receive the packet while a host processor of the heterogeneous computing platform is in a low-power state.

7 . The IHS of claim 6 , wherein the low-power state comprises an Advanced Configuration and Power Interface (ACPI) G3 state.

8 . An Information Handling System (IHS), comprising:

a heterogeneous computing platform; and

an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into or coupled to the heterogeneous computing platform, wherein the OOB MCU is configured to receive, from a cloud service, a packet stored in a command buffer associated with the IHS, and wherein the packet comprises at least one of: a baseline packet, or an opaque packet;

wherein the opaque packet is assembled using a map, key, or decode ring known to an Original Equipment Manufacturer (OEM) of the IHS and at least partially unknown to a manufacturer of the heterogeneous computing platform.

9 . The IHS of claim 8 , wherein the opaque packet comprises an identifier portion configured to indicate whether the packet is opaque.

10 . The IHS of claim 8 , wherein the opaque packet comprises a header portion configured with heterogeneous computing platform device routing information.

11 . The IHS of claim 8 , wherein the opaque packet enables remote management of the IHS.

12 . A method, comprising:

receiving, from an Information Technology Decision Maker (ITDM) terminal, an Out-of-Band (OOB) command configured to enable remote management of an Information Handling System (IHS) comprising a heterogeneous computing platform;

including an indication of the OOB command in an OOB packet, wherein including the indication of the OOB command in the OOB packet comprises creating a baseline packet in response to the OOB command invoking a feature provided or

supported by a manufacturer of the heterogeneous computing platform; and

storing the OOB packet in a command buffer associated with the IHS in response to the IHS being in a low-power state.

13 . The method of claim 12 , wherein including the indication of the OOB command in the OOB packet further comprises using a map, key, or decode ring known to the manufacturer of the heterogeneous computing platform.

14 . The method of claim 12 , wherein the baseline packet is created using a map, key, or decode ring.

15 . The method of claim 12 , wherein the baseline packet is created using a map, key, or decode ring known to the manufacturer of the heterogeneous computing platform.

16 . The method of claim 12 , wherein the low-power state comprises an Advanced Configuration and Power Interface (ACPI) G3 state.