Offloading video coding processes to hardware for better density-quality tradeoffs
Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
1 . A method for video processing, comprising:
determining a target video quality and a target latency for an input video;
encoding, using a hardware encode module, the input video, in response to determining that the target video quality is met by a quality metric attainable by the hardware encode module and the target latency is met by a latency attainable by the hardware encode module;
determining that multiple passes are needed to meet a further target video quality of the input video;
performing, using the hardware encode module, a first encode pass of the multiple passes; and
performing, using software, a final encode pass of the multiple passes.
2 . The method of claim 1 , wherein one or more of the target video quality, the target latency, and the further target video quality are predefined based on a coding context of the input video.
3 . The method of claim 2 , wherein the coding context includes one of: video on demand content, broadcast content, premium over the top content, live streaming content, and real-time gaming content.
4 . The method of claim 1 , wherein one or more of the target video quality, the target latency, and the further target video quality are predefined based on a type of coding content.
5 . The method of claim 1 , wherein the hardware encode module is an application-specific integrated circuit.
6 . The method of claim 1 , wherein the hardware encode module is a part of a System-on-a-Chip.
7 . The method of claim 1 , further comprising:
decoding, using the hardware encode module, the input video.
8 . The method of claim 1 , wherein the final encode pass is a second encode pass of the multiple passes.
9 . The method of claim 1 , further comprising:
generating an encoded bitstream based on the multiple passes, wherein the encoded bitstream is H.264 compliant.
10 . The method of claim 1 , further comprising:
generating an encoded bitstream based on the multiple passes, wherein the encoded bitstream is VP9 compliant.
11 . The method of claim 1 , further comprising:
generating an encoded bitstream based on the multiple passes, wherein the encoded bitstream is AV1 compliant.
12 . An apparatus, comprising:
a memory to store instructions; and
one or more processors to execute the instructions, wherein the instructions, when executed by the one or more processors, cause the one or more processors to:
determine a target video quality and a target latency for an input video;
command a hardware encode module to encode the input video, in response to determining that the target video quality is met by a quality metric attainable by the hardware encode module and the target latency is met by a latency attainable by the hardware encode module;
determine that multiple passes are needed to meet a further target video quality;
command the hardware encode module to perform a first encode pass of the multiple passes; and
command software to perform a final encode pass of the multiple passes.
13 . The apparatus of claim 12 , wherein one or more of the target video quality, the target latency, and the further target video quality are predefined based on a coding context of the input video.
14 . The apparatus of claim 13 , wherein the coding context includes one of: video on demand, broadcast, premium over the top, live streaming, and online gaming.
15 . The apparatus of claim 12 , wherein one or more of the target video quality, the target latency, and the further target video quality are predefined based on a type of coding content.
16 . The apparatus of claim 12 , wherein the instructions further cause the one or more processors to:
command the hardware encode module to decode the input video.
17 . The apparatus of claim 12 , wherein the final encode pass is a second encode pass of the multiple passes.
18 . The apparatus of claim 12 , wherein the instructions further cause the one or more processors to:
generate an encoded bitstream based on the multiple passes, wherein the encoded bitstream is H.264 compliant.
19 . The apparatus of claim 12 , wherein the instructions further cause the one or more processors to:
generate an encoded bitstream based on the multiple passes, wherein the encoded bitstream is VP9 compliant.
20 . The apparatus of claim 12 , wherein the instructions further cause the one or more processors to:
generate an encoded bitstream based on the multiple passes, wherein the encoded bitstream is AV1 compliant.