Motion vector determination with CMOS
A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.
1 . A solid state drive, comprising:
a memory device;
a first complementary metal oxide semiconductor (CMOS) coupled to the memory device; and
a controller coupled to the memory device, wherein the controller is separate and distinct from the first CMOS and memory device, wherein the first CMOS comprises one or more processors, memories, and an error correction code (ECC) engine, wherein the ECC engine includes a format check, a tunable ECC encoder, and a tunable ECC decoder, wherein the controller is configured to execute computer-readable instructions that when executed cause the controller to:
receive at least a portion of a first I-frame comprising a first macroblock and second I-frame comprising a second macroblock, on the memory device, wherein the memory device comprises a NAND die;
store the portion of the first I-frame with a first amount of error correction code (ECC) data;
correlate the first macroblock to the second macroblock;
determine a first motion vector of the first macroblock and a second motion vector of the second macroblock;
encode a P-frame based on the first I-frame and the first motion vector, wherein the encoding comprises encoding the P-frame with a second amount of ECC data, wherein the first amount of ECC data is greater than the second amount of ECC data; and
either:
reorder the first macroblock and second macroblock to physically locate each on the NAND die; or
duplicate information of the first macroblock and second macroblock and cause the duplicate information to be physically located on the NAND die.
2 . The solid state drive of claim 1 , wherein the instruction that causes the controller to correlate the first macroblock to the second macroblock is executed by the first CMOS.
3 . The solid state drive of claim 2 , wherein the first macroblock and second macroblock comprise an image, further comprising computer-readable instructions to cause the controller to calculate a shift of position of the image as between the first macroblock and second macroblock based on one of the first motion vector and second motion vector.
4 . The solid state drive of claim 2 , further comprising a second CMOS, wherein the computer-readable instructions that cause the controller to determine the first and second motion vectors, further cause the first motion vector to be determined on the first CMOS, and the second motion vector to be determined on the second CMOS.
5 . The solid state drive of claim 4 , wherein the computer-readable instructions further cause the controller to encode a B-frame based on at least the first I-frame, second I-frame, or P-frame.
6 . The solid state drive of claim 1 , wherein the computer-readable instructions further cause the controller to adjust one of a code rate or parity bits, based on the first I-frame, second I-frame, P-frame, or B-frame.