Adaptive gain readout for voltage domain global shutter

1 . An adaptive analog to digital converter (ADC) gain controller circuit for use in a Voltage Domain Global Shutter (VDGS) image sensor, comprising:

a pixel level connection coupled to a pixel cell;

a reset transistor coupled between a supply voltage and the pixel level connection;

a source follower transistor having a gate coupled to the pixel level connection;

a row select transistor coupled between the source follower transistor and a bitline;

a reset switch transistor coupled to the pixel level connection;

a reset storage capacitor coupled between the reset switch transistor and ground to receive a reset voltage of the pixel cell;

a signal switch transistor coupled to the pixel level connection;

a signal storage capacitor coupled between the signal switch transistor and ground to receive a signal voltage of the pixel cell;

a G-hat unit coupled to the bitline;

a gain stage comprising a first input coupled to the bitline, a second input coupled to an output of the G-hat unit, a third input coupled to a ramp voltage, a first output coupled to a positive input terminal of an ADC comparator, a second output coupled to a negative input terminal of the ADC comparator, wherein the gain stage comprises more than one gain factor under control of the second input and a high gain factor serves as its initially default factor; and

an ADC counter coupled between an output of the ADC comparator and an digital output of the ADC.

2 . The adaptive ADC gain controller circuit of claim 1 , further comprising:

a current source coupled between the bitline and ground;

a ramp generator with an output coupled to the third input of the gain stage to supply the ramp voltage;

a G-hat comparator coupled as an input stage of the G-hat unit, wherein the G-hat comparator with a negative input terminal coupled to the bitline and a positive input terminal coupled to a threshold voltage, and wherein an output of the G-hat comparator is determined to be high if a voltage on the bitline is lower than a voltage of the threshold voltage;

a G-hat latch coupled as an output stage of the G-hat unit, wherein the output of the G-hat comparator is latched into the G-hat latch under control of a latch enable signal, and wherein an output of the G-hat latch is an output of the G-hat unit; and

an auto-zero signal coupled to the ADC comparator to preset the ADC comparator.

3 . The adaptive ADC gain controller circuit of claim 2 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance;

a second capacitor coupled between the third input of the gain stage and the first output of the gain stage; and

a ground coupled to the second output of the gain stage.

4 . The adaptive ADC gain controller circuit of claim 3 , wherein the second capacitor changes its capacitance under control of the second input, and wherein the variable capacitance of the second capacitor is changed in a way which leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

5 . The adaptive ADC gain controller circuit of claim 2 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance; and

a second capacitor coupled between the third input of the gain stage and the second output of the gain stage.

6 . The adaptive ADC gain controller circuit of claim 5 , wherein the second capacitor changes its capacitance under control of the second input, and wherein the variable capacitance of the second capacitor is changed in a way which leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

7 . The adaptive ADC gain controller circuit of claim 2 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and a negative input terminal of an operational amplifier (OpAmp), wherein the first capacitor is a capacitor with a fixed capacitance;

a second capacitor coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp, wherein the second capacitor is a capacitor with a fixed capacitance;

a third capacitor coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp, wherein the third capacitor is a capacitor with a fixed capacitance;

a fourth capacitor coupled between the output terminal of the OpAmp and the first output of the gain stage;

a gain control switch coupled between the negative input terminal of the OpAmp and the third capacitor; and

a gain reset switch coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp to reset the gain stage.

8 . The adaptive ADC gain controller circuit of claim 7 , wherein the third capacitor is connected in parallel to the second capacitor if the gain control switch is turned on by a high voltage of the second input, and wherein the combined capacitance of the second capacitor and the third capacitor leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

9 . A method of setting a gain factor adaptively to prepare for an analog-to-digital converter (ADC) operation, comprising:

generating a voltage pulse to turn a reset transistor on and off to reset a pixel line voltage to a supply voltage, after a reset voltage being sampled from a pixel cell and stored into a reset capacitor through a reset access switch firstly and a signal voltage being sampled from a pixel cell and stored into a signal capacitor through a signal access switch secondly;

presetting a gain factor of a gain stage of the ADC to a high value;

turning both the signal access switch and a row select transistor on to read the stored signal voltage from the signal capacitor to a bitline;

setting an output of a G-hat unit to a high voltage if the signal voltage read on to the bitline is determined to be lower than a threshold voltage;

setting the gain factor of a gain stage of the ADC to a low value if the output of the G-hat unit is a high voltage;

generating an auto-zero (AZ) voltage pulse to turn an ADC comparator on and off, to reset the ADC;

receiving the signal voltage from the bitline to couple to an input of the gain stage of the ADC;

converting the signal voltage at the input of the gain stage to a digital signal value by the ADC;

turning the signal access switch off;

turning the reset access switch on to read the stored reset voltage from the reset capacitor to the bitline; and

converting the reset voltage at the input of the gain stage to a digital reset value by the ADC.

10 . The method of setting a gain factor adaptively to prepare for an ADC operation of claim 9 , wherein a reset control signal to control the reset transistor, a reset access switch control signal to control the reset access switch, a signal access switch control signal to control the signal access switch, a row select control signal to control the row select transistor, and the AZ voltage pulse are controlled by a control circuit.

11 . A gain adaptive readout circuit for Voltage Domain Global Shutter (VDGS) imaging system, comprising:

a pixel array including a plurality of pixel cells arranged in rows and columns, wherein each of the pixel cells is coupled to generate image charge in response to incident light and to convert image charge into image voltage;

a gain adaptive readout circuit coupled to the pixel array, wherein the gain adaptive readout circuit comprises:

a pixel level connection coupled to a pixel cell;

a reset transistor coupled between a supply voltage and the pixel level connection;

a source follower transistor having a gate coupled to the pixel level connection;

a row select transistor coupled between the source follower transistor and a bitline;

a reset switch transistor coupled to the pixel level connection;

a reset storage capacitor coupled between the reset switch transistor and ground to receive a reset voltage of the pixel cell;

a signal switch transistor coupled to the pixel level connection;

a signal storage capacitor coupled between the signal switch transistor and ground to receive a signal voltage of the pixel cell;

a G-hat unit coupled to the bitline;

a gain stage comprising a first input coupled to the bitline, a second input coupled to an output of the G-hat comparator, a third input coupled to a ramp voltage, a first output coupled to a positive input terminal of an ADC comparator, and a second output coupled to a negative input terminal of the ADC comparator, wherein the gain stage comprises more than one gain factors under control of the second input and a high gain factor serves as its initially default factor; and

an ADC counter coupled between an output of the ADC comparator and an digital output of the ADC.

12 . The gain adaptive readout circuit for VDGS imaging system of claim 11 , further comprising:

a current source coupled between the bitline and ground;

a ramp generator with an output coupled to the third input of the gain stage to supply the ramp voltage;

a G-hat comparator coupled as an input stage of the G-hat unit, wherein the G-hat comparator with a negative input terminal coupled to the bitline and a positive input terminal coupled to a threshold voltage, and wherein an output of the G-hat comparator is determined to be high if a voltage on the bitline is lower than a voltage of the threshold voltage;

a G-hat latch coupled as an output stage of the G-hat unit, wherein the output of the G-hat comparator is latched into the G-hat latch under control of a latch enable signal, and wherein an output of the G-hat latch is an output of the G-hat unit;

an auto-zero signal coupled to the ADC comparator to preset the ADC comparator;

a control circuit coupled to control operation of the pixel array, the gain adaptive readout circuit, the current source, the ramp generator, and the G-hat unit; and

a function circuit coupled to the digital output of the ADC to store digital values of the image charge from the pixel array.

13 . The gain adaptive readout circuit for VDGS imaging system of claim 12 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance;

a second capacitor coupled between the third input of the gain stage and the first output of the gain stage; and

a ground coupled to the second output of the gain stage.

14 . The gain adaptive readout circuit for VDGS imaging system of claim 13 , wherein the second capacitor changes its capacitance under control of the second input, and wherein the variable capacitance of the second capacitor is changed in a way which leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

15 . The gain adaptive readout circuit for VDGS imaging system of claim 12 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance; and

a second capacitor coupled between the third input of the gain stage and the second output of the gain stage.

16 . The gain adaptive readout circuit for VDGS imaging system of claim 15 , wherein the second capacitor changes its capacitance under control of the second input, and wherein the variable capacitance of the second capacitor is changed in a way which leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

17 . The gain adaptive readout circuit for VDGS imaging system of claim 12 , wherein the gain stage comprises:

a first capacitor coupled between the first input of the gain stage and a negative input terminal of an operational amplifier (OpAmp), wherein the first capacitor is a capacitor with a fixed capacitance;

a second capacitor coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp, wherein the second capacitor is a capacitor with a fixed capacitance;

a third capacitor coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp, wherein the third capacitor is a capacitor with a fixed capacitance;

a fourth capacitor coupled between the output terminal of the OpAmp and the first output of the gain stage;

a gain control switch coupled between the negative input terminal of the OpAmp and the third capacitor; and

a gain reset switch coupled between the negative input terminal of the OpAmp and an output terminal of the OpAmp to reset the gain stage.

18 . The gain adaptive readout circuit for VDGS imaging system of claim 17 , wherein the third capacitor is connected in parallel to the second capacitor if the gain control switch is turned on by a high voltage of the second input, and wherein the combined capacitance of the second capacitor and the third capacitor leads to the reduction of the gain factor of the gain stage from its initially set high value to a lower value if the output of the G-hat unit is determined to be high.

19 . The gain adaptive readout circuit for VDGS imaging system of claim 12 , wherein the threshold voltage, the latch enable signal, and the auto-zero signal are under control of the control circuit.