IP Library › Granted Patent US 12,666,585
Granted Patent B2
US 12,666,585 · App. 18/224,810 · Granted Jun 23, 2026

Semiconductor device

Inventors: Dian-Sheng Yu (Hsinchu, TW); Jhon-Jhy Liaw (Hsinchu, TW); Kuo-Hua Pan (Hsinchu, TW); Chia-He Chung (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10B10/12
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Quick Facts
Patent No.
US 12,666,585
App. No.
18/224,810
Granted
Jun 23, 2026
Kind
B2
Abstract

A semiconductor device is provided. The semiconductor device includes a first pull-down transistor, a first pull-up transistor, a second pull-down transistor, a second pull-up transistor, a first pass gate transistor, a second pass gate transistor, a first bit line, a second bit line, a word line and a voltage supply line. The first pull-down transistor and the first pull-up transistor form a first inverter. The second pull-down transistor and the second pull-up transistor form a second inverter. An input of the first inverter is connected to an output of the second inverter through a first node butted contact. The first node butted contact includes a metal contact directly contacted a gate of the first pull-down transistor and the first pull-up transistor and directly contacted a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

Claims (53)

1 . A semiconductor device, comprising:

a first pull-down transistor;

a first pull-up transistor, wherein the first pull-down transistor and the first pull-up transistor form a first inverter;

a second pull-down transistor;

a second pull-up transistor, wherein the second pull-down transistor and the second pull-up transistor form a second inverter, an input of the first inverter is connected to an output of the second inverter through a first node butted contact, and an output of the first inverter is connected to an input of the second inverter through a second node butted contact;

a first pass gate transistor, connected to the second node butted contact;

a second pass gate transistor, connected to the first node butted contact;

a first bit line, connected to the first pass gate transistor;

a second bit line, connected to the second pass gate transistor;

a word line, connected to the first pass gate transistor and the second pass gate transistor; and

a voltage supply line, connected to the first pull-up transistor and the second pull up transistor;

wherein the first node butted contact includes a metal contact overlapping a gate of the first pull-down transistor and the first pull-up transistor and overlapping a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor, and the gate of the first pull-down transistor and the first pull-up transistor is substantially parallel to the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

2 . The semiconductor device according to claim 1 , wherein the metal contact directly contacts the gate of the first pull-down transistor and the first pull-up transistor and directly contacts the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

3 . The semiconductor device according to claim 1 , wherein an overlapping area of the metal contact overlapping the gate of the first pull-down transistor and the first pull-up transistor is substantially equal to an overlapping area of the metal contact overlapping the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

4 . The semiconductor device according to claim 1 , wherein a width of the metal contact is substantially uniform.

5 . The semiconductor device according to claim 1 , wherein only part of the metal contact overlaps the gate of the first pull-down transistor and the first pull-up transistor.

6 . The semiconductor device according to claim 1 , wherein only part of the metal contact overlaps the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

7 . The semiconductor device according to claim 1 , wherein the metal contact is long slot shaped.

8 . The semiconductor device according to claim 7 , wherein one end of the metal contact is located above the gate of the first pull-down transistor and the first pull-up transistor.

9 . The semiconductor device according to claim 7 , wherein one end of the metal contact is located above the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

10 . A semiconductor device, comprising:

a first pull-down transistor;

a first pull-up transistor, wherein the first pull-down transistor and the first pull-up transistor form a first inverter;

a second pull-down transistor;

a second pull-up transistor, wherein the second pull-down transistor and the second pull-up transistor form a second inverter, an input of the first inverter is connected to an output of the second inverter through a first node butted contact and an output of the first inverter is connected to an input of the second inverter through a second node butted contact;

a first pass gate transistor, connected to the second node butted contact;

a second pass gate transistor, connected to the first node butted contact;

a first bit line, connected to the first pass gate transistor;

a second bit line, connected to the second pass gate transistor;

a word line, connected to the first pass gate transistor and the second pass gate transistor; and

a voltage supply line, connected to the first pull-up transistor and the second pull up transistor;

wherein the first node butted contact includes a metal contact connected to a gate of the first pull-down transistor and the first pull-up transistor and connected to a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor, and the gate of the first pull-down transistor and the first pull-up transistor has an enlarged terminal, and the gate of the first pull-down transistor and the first pull-up transistor is substantially parallel to the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

11 . The semiconductor device according to claim 10 , wherein the enlarged terminal of the gate is 1.1 to 1.5 times as wide as a body of the gate.

12 . The semiconductor device according to claim 10 , wherein the enlarged terminal of the gate is located at outside of a voltage supply line.

13 . The semiconductor device according to claim 10 , wherein the metal contact directly contacts the gate of the first pull-down transistor and the first pull-up transistor and directly contacts the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

14 . The semiconductor device according to claim 10 , wherein an overlapping area of the metal contact overlapping the gate of the first pull-down transistor and the first pull-up transistor is smaller than an overlapping area of the metal contact overlapping the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

15 . The semiconductor device according to claim 10 , wherein only part of the metal contact overlaps the gate of the first pull-down transistor and the first pull-up transistor.

16 . The semiconductor device according to claim 10 , wherein only part of the metal contact overlaps the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

17 . A semiconductor device, comprising:

a first pull-down transistor;

a first pull-up transistor, wherein the first pull-down transistor and the first pull-up transistor form a first inverter;

a second pull-down transistor;

a second pull-up transistor, wherein the second pull-down transistor and the second pull-up transistor form a second inverter, an input of the first inverter is connected to an output of the second inverter through a first node butted contact, and an output of the first inverter is connected to an input of the second inverter through a second node butted contact;

a first pass gate transistor, connected to the second node butted contact;

a second pass gate transistor, connected to the first node butted contact;

a first bit line, connected to the first pass gate transistor;

a second bit line, connected to the second pass gate transistor;

a word line, connected to the first pass gate transistor and the second pass gate transistor; and

a voltage supply line, connected to the first pull-up transistor and the second pull up transistor;

wherein the first node butted contact includes a metal contact directly contacting a gate of the first pull-down transistor and the first pull-up transistor and directly contacting a source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor, and the gate of the first pull-down transistor and the first pull-up transistor is substantially parallel to the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

18 . The semiconductor device according to claim 17 , wherein only part of the metal contact overlaps the gate of the first pull-down transistor and the first pull-up transistor.

19 . The semiconductor device according to claim 17 , wherein only part of the metal contact overlaps the source/drain of the second pull-down transistor, the second pull-up transistor and the second pass gate transistor.

20 . The semiconductor device according to claim 17 , wherein one end of the metal contact is located above the gate of the first pull-down transistor and the first pull-up transistor.