Semiconductor device with gate-cut structure and fabrication methods thereof

1 . A method of forming a semiconductor structure, comprising:

forming a fin over a semiconductor substrate;

forming an isolation region on sidewalls of the fin;

forming a metal gate over the fin and the isolation region;

etching the metal gate to form a trench through the isolation region, wherein the trench exposes a top portion of the semiconductor substrate;

passivating the top portion of the semiconductor substrate to form a dielectric layer at a bottom of the trench; and

depositing a dielectric material in the trench to form a dielectric structure, wherein the dielectric structure divides the metal gate into two sections.

2 . The method of claim 1 , wherein the passivating of the top portion of the semiconductor substrate is an oxidization process, and the dielectric layer is an oxide layer.

3 . The method of claim 2 , wherein the oxidization process is an O 2 plasma process.

4 . The method of claim 1 , wherein the trench is directly above an interface between an N-type well region and a P-type well region of the semiconductor substrate.

5 . The method of claim 1 , further comprising:

after the etching of the metal gate to form the trench, implanting a dopant into the top portion of the semiconductor substrate through the trench.

6 . The method of claim 5 , wherein the dopant is boron.

7 . The method of claim 5 , wherein the implanting of the dopant creates a depletion region under the dielectric layer.

8 . The method of claim 1 , wherein the etching of the metal gate includes a first etching step and a second etching step that differs from the first etching step.

9 . The method of claim 8 , wherein the first etching step includes a cyclic etching operation, and the second etching step includes a single etching operation.

10 . The method of claim 8 , wherein the second etching step produces a polymer byproduct, and the first etching step is free of producing the polymer byproduct.

11 . A method of forming a semiconductor structure, comprising:

patterning a top portion of a substrate to form a first fin and a second fin;

after the patterning of the top portion of the substrate to form the first fin and the second fin, recessing a region of the substrate between the first fin and the second fin to form a trench, wherein the trench exposes an interface between a first-type well region and a second-type well region of the substrate, wherein the first-type well region and the second-type well region are of opposite conductivity types;

depositing an isolation layer between the first fin and the second fin and filling the trench;

forming a metal gate over the first fin and the second fin;

etching the metal gate to form a recess through the metal gate and extending into the trench; and

depositing a dielectric material in the recess to form a dielectric structure that divides the metal gate into a first section over the first fin and a second section over the second fin.

12 . The method of claim 11 , wherein a bottommost portion of the dielectric structure is separated from the first-type well region and the second-type well region by a portion of the isolation layer in the trench.

13 . The method of claim 11 , further comprising:

forming a first epitaxial structure on the first fin and a second epitaxial structure on the second fin,

wherein a first portion of the dielectric structure laterally between the first section and the second section of the metal gate has a first height, a second portion of the dielectric structure laterally between the first epitaxial structure and the second epitaxial structure has a second height, and the first height is larger than the second height.

14 . The method of claim 11 , wherein the etching of the metal gate includes a first etching step and a second etching step that is weaker than the first etching step.

15 . The method of claim 14 , wherein the first etching step includes a cyclic etching operation, and the second etching step includes a single etching operation.

16 . The method of claim 11 , wherein the first section of the metal gate and the first fin forms a pass-gate transistor of a memory cell, and the second section of the metal gate and the second fin forms a pull-up transistor of the memory cell.

17 . A semiconductor device, comprising:

a first gate electrode across a first fin over a first-type well region of a semiconductor substrate;

a second gate electrode across a second fin over a second-type well region of the semiconductor substrate, wherein the first-type well region and the second-type well region have opposite conductivity types;

an isolation layer disposed over the semiconductor substrate and on sidewalls of the first fin and the second fin;

a gate-cut structure separating the first gate electrode from the second gate electrode, wherein the gate-cut structure extends through the isolation layer; and

a dielectric layer disposed on the gate-cut structure and separating the gate-cut structure from the semiconductor substrate, wherein the dielectric layer is below a bottom surface of the isolation layer.

18 . The semiconductor device of claim 17 , further comprising:

a depletion region stacked between the dielectric layer and the semiconductor substrate.

19 . The semiconductor device of claim 18 , wherein the dielectric layer and the depletion region are implanted with boron.

20 . The semiconductor device of claim 17 , wherein the gate-cut structure has a first portion directly above the isolation layer and a second portion directly above an interface between the first-type well region and the second-type well region, the first portion has a first height and the second portion has a second height that is larger than the first height.