Method for preparing semiconductor structure, semiconductor structure and semiconductor memory

1 . A semiconductor structure, comprising:

a substrate;

a stack structure formed on the substrate, wherein the stack structure comprises a plurality of channel areas, first source-drain areas and second source-drain areas, each channel area is configured to extend in a second direction, each first source-drain area and each second source-drain area are configured to extend in a first direction, and each first source-drain area and each second source-drain area are located on a same side of each channel area;

a first source-drain structure formed in each first source-drain area and a second source-drain structure formed in each second source-drain area, wherein both the first source-drain structure and the second source-drain structure are configured to extend in the first direction; and

wherein in each of the channel areas, the stack structure comprises:

a substrate isolation layer;

at least one stack layer formed on the substrate isolation layer; and

a support layer formed on the at least one stack layer

wherein each stack layer in each channel area comprises a further support layer, a first isolation layer, a gate structure, a channel structure and a second isolation layer, the gate structure comprises the channel structure, a gate dielectric layer formed on a surface of the channel structure, and a gate conductive layer formed on a surface of the gate dielectric layer.

2 . The semiconductor structure of claim 1 , wherein

materials of the channel structure, the first source-drain structure, and the second source-drain structure comprises at least one of: indium oxide, zinc oxide, indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium zinc tin oxide, or zinc oxynitride.

3 . The semiconductor structure of claim 1 , wherein

each stack layer in each first source-drain area comprises the further support layer, the first isolation layer formed on the further support layer, a first protective layer formed on the first isolation layer, the first source-drain structure formed on the first protective layer, a second protective layer formed on the first source-drain structure, and the second isolation layer formed on the second protective layer; and

each stack layer in each second source-drain area comprises the further support layer, the first isolation layer formed on the further support layer, the first protective layer formed on the first isolation layer, the second source-drain structure formed on the first protective layer, the second protective layer formed on the second source-drain structure, and the second isolation layer formed on the second protective layer.

4 . The semiconductor structure of claim 3 , wherein

the stack structure further comprises a plurality of capacitor areas and word line areas, each capacitor area is configured to extend in the first direction, and is connected to each first source-drain area, each word line area is located on a side, far away from each capacitor area, of each channel area, and is connected to each channel area.

5 . The semiconductor structure of claim 4 , wherein

the semiconductor structure further comprises a plurality of third isolation layers, each third isolation layer is formed on surfaces of the channel structure, the first isolation layer, the second isolation layer, and the support layer;

a part of each third isolation layer formed in each channel area is configured as the gate dielectric layer;

each stack layer in each word line area comprises: the support layer, the third isolation layer and a word line; and

the word line is formed between adjacent third isolation layers and is connected to the gate structure,

wherein the semiconductor structure further comprises a plurality of support structures, the support structures are configured to divide the stack structure into the channel areas, the first source-drain areas and the second source-drain areas.

6 . The semiconductor structure of claim 5 , further comprising

a plurality of first metal pillars, wherein each first metal pillar is configured to extend in the first direction;

a part of each first metal pillar that is formed between the first protective layer and the second protective layer in each first source-drain area is configured as a first electrode structure and is connected to the first source-drain structure, and

the other part of each first metal pillar that is formed in the capacitor area is configured as a lower electrode layer, a dielectric layer is formed on a surface of the lower electrode layer, an upper electrode layer is formed on a surface of the dielectric layer; and a filling structure is formed in voids that are formed by the upper electrode layer.

7 . The semiconductor structure of claim 6 , further comprising

a plurality of bit lines and a plurality of second metal pillars, wherein

each bit line is configured to extend in a third direction; and

each second metal pillar is configured to extend in the first direction, a part of each second metal pillar is formed between the first protective layer and the second protective layer located in each second source-drain area and is connected to each second source-drain area, and the other part of each second metal pillar is formed in the bit line,

wherein the gate conductive layer, the gate dielectric layer, and the channel structure form a gate structure, a plurality of gate structures are arranged in the second direction, the semiconductor structure further comprises a plurality of dividing structures, and the dividing structures are configured to isolate the gate structures.