Semiconductor memory device and method of fabricating the same
A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.
1 . A semiconductor memory device, comprising:
a stack structure including layer groups that are stacked on a substrate in a vertical direction perpendicular to a top surface of the substrate, the layer groups each including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and
a bit line on one side of the stack structure, the bit line extending lengthwise in the vertical direction,
wherein the word line of each of the layer groups extends in a first direction parallel to the top surface of the substrate,
wherein the layer groups include a first layer group and a second layer group stacked on the first layer group in the vertical direction,
wherein the channel layer of the first layer group is below the word line of the first layer group in the vertical direction,
wherein the channel layer of the second layer group is above the word line of the second layer group in the vertical direction, and
wherein the bit line includes:
a first protrusion portion connected to the channel layer of the first layer group; and
a second protrusion portion connected to the channel layer of the second layer group.
2 . The device as claimed in claim 1 , wherein:
the layer groups further include a third layer group stacked on the second layer group,
the channel layer of the third layer group is below the word line of the third layer group, and
the channel layer of the third layer group is connected to the second protrusion portion.
3 . The device as claimed in claim 2 , wherein a first vertical interval between the word line of the first layer group and the word line of the second layer group is different from a second vertical interval between the word line of the second layer group and the word line of the third layer group.
4 . The device as claimed in claim 1 , wherein a structure of the word line and the channel layer of the first layer group and a structure of the word line and the channel layer of the second layer group are mirror-symmetrical to each other about a central line between the first layer group and the second layer group.
5 . The device as claimed in claim 1 ,
wherein the word line of each layer group of the layer groups includes:
a gate portion that overlaps the channel layer; and
a connection portion that connects the gate portions that are adjacent to each other in the first direction, and
wherein a width of the gate portion is greater than a width of the connection portion, as measured in a second direction that crosses the first direction.
6 . The device as claimed in claim 1 , wherein the channel layer of each layer group of the layer groups includes an amorphous oxide semiconductor or a two-dimensional semiconductor.
7 . The device as claimed in claim 1 , wherein:
the bit line further includes a pad at a top of the bit line, and
a bit-line contact is connected to the pad.
8 . The device as claimed in claim 1 , wherein the data storage element in each of the layer groups includes:
a first electrode electrically connected to the channel layer;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode.
9 . The device as claimed in claim 1 , wherein:
the word lines of the layer groups extend to a connection region of the substrate,
the word lines include corresponding pad portions on the connection region,
the pad portions constitute a stepwise structure on the connection region,
the pad portions are sequentially exposed in a downward direction by the stepwise structure, and
a thickness of each of the pad portions is greater than a thickness of the corresponding word line.
10 . The device as claimed in claim 1 , further comprising:
a peripheral circuit layer between the substrate and the stack structure; and
a through contact that electrically connects at least one selected from the word line and the bit line to the peripheral circuit layer.
11 . A semiconductor memory device, comprising:
a stack structure including layer groups that are stacked on a substrate in a vertical direction perpendicular to a top surface of the substrate, the layer groups each including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and
a bit line on one side of the stack structure, the bit line extending lengthwise in the vertical direction,
wherein the word line of each of the layer groups extends lengthwise in a horizontal direction that is parallel to the top surface of the substrate,
wherein the layer groups include a first layer group, a second layer group, and a third layer group that are sequentially stacked in the vertical direction,
wherein a first vertical interval between the channel layer of the first layer group and the channel layer of the second layer group is different from a second vertical interval between the channel layer of the second layer group and the channel layer of the third layer group, and
wherein the channel layer of the first layer group, the channel layer of the second layer group, and the channel layer of the third layer group are spaced apart from each other in the vertical direction.
12 . The device as claimed in claim 11 , wherein the bit line includes:
a first protrusion portion connected to the channel layer of the first layer group; and
a second protrusion portion connected in common to the channel layer of the second layer group and the channel layer of the third layer group.
13 . The device as claimed in claim 11 , wherein the first vertical interval is greater than the second vertical interval.
14 . The device as claimed in claim 11 , wherein:
the word line of the first layer group and the word line of the second layer group are between the channel layer of the first layer group and the channel layer of the second layer group, and
an insulating layer is between the channel layer of the second layer group and the channel layer of the third layer group.
15 . The device as claimed in claim 11 , wherein a third vertical interval between the word line of the first layer group and the word line of the second layer group is different from a fourth vertical interval between the word line of the second layer group and the word line of the third layer group.
16 . A semiconductor memory device, comprising:
a stack structure including layer groups that are stacked on a substrate in a vertical direction that is perpendicular to a top surface of the substrate, the layer groups each including a word line, a channel layer adjacent to the word line, and a data storage element electrically connected to the channel layer; and
a bit line on one side of the stack structure, the bit line extending lengthwise in the vertical direction,
wherein the bit line electrically connects the layer groups,
wherein the channel layer is between the bit line and the data storage element in the vertical direction,
wherein the layer groups include a first layer group, a second layer group, and a third layer group that are sequentially stacked in the vertical direction,
wherein the first layer group is configured such that the word line of the first layer group is above a top surface of the channel layer of the first layer group in the vertical direction,
wherein the second layer group is configured such that the word line of the second layer group is below a bottom surface of the channel layer of the second layer group in the vertical direction,
wherein a structure of the first layer group and a structure of the second layer group are mirror-symmetrical to each other about a central line between the first layer group and the second layer group, and
wherein a structure of the third layer group is the same as the structure of the first layer group.
17 . The device as claimed in claim 16 , wherein the channel layer of each of the layer groups includes an amorphous oxide semiconductor or a two-dimensional semiconductor.
18 . The device as claimed in claim 16 , wherein the bit line includes a plurality of protrusion portions connected with the layer groups.
19 . The device as claimed in claim 16 ,
wherein the third layer group is configured such that the word line of the third layer group is above a top surface of the channel layer of the third layer group in the vertical direction.
20 . The device as claimed in claim 16 , wherein the data storage element of each of the layer groups includes:
a first electrode electrically connected to the channel layer;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode.