Memory devices having vertical transistors and fabricating methods thereof
A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.
1 . A semiconductor device, comprising:
an array of memory cells, each memory cell comprising:
a capacitor; and
a vertical transistor comprising:
a semiconductor body extending in a vertical direction, comprising a curved sidewall and a flat sidewall, and in contact with the capacitor, and
a three-sided gate structure surrounding the semiconductor body from three lateral directions.
2 . The semiconductor device of claim 1 , wherein:
the three-sided gate structure surrounds the curved sidewall of the semiconductor body.
3 . The semiconductor device of claim 2 , further comprising:
a gate dielectric layer between the three-sided gate structure and the curved sidewall of the semiconductor body.
4 . The semiconductor device of claim 1 , wherein:
the three-sided gate structures of a row of the vertical transistors along a first lateral direction are connected with each other to form a word line extending along the first lateral direction, and the three lateral directions include at least two opposite lateral directions along the first lateral direction.
5 . The semiconductor device of claim 4 , further comprising:
a plurality of first and second spacers each extending along the first lateral direction between rows of the vertical transistors.
6 . The semiconductor device of claim 4 , wherein:
a plurality of first and second spacers are alternatively arranged along a second lateral direction perpendicular to the first lateral direction.
7 . The semiconductor device of claim 6 , wherein:
each first spacer is located between the curved sidewalls of the semiconductor bodies of two adjacent rows of vertical transistors.
8 . The semiconductor device of claim 6 , wherein:
each second spacer is located between the flat sidewalls of the semiconductor bodies of two adjacent rows of vertical transistors.
9 . The semiconductor device of claim 6 , wherein:
the semiconductor bodies are aligned along the second lateral direction.
10 . The semiconductor device of claim 6 , wherein:
the semiconductor bodies are aligned along a third lateral direction with a non-zero angle with respect to the first lateral direction.
11 . The semiconductor device of claim 6 , further comprising:
a plurality of bit lines arranged in parallel along the second lateral direction,
wherein the capacitors are connected to first ends of the semiconductor bodies, and the bit lines are connected to second ends of the semiconductor bodies opposite to the first ends.
12 . A memory system, comprising:
an array of memory cells, each memory cell comprising:
a capacitor; and
a vertical transistor comprising:
a semiconductor body extending in a vertical direction and in contact with the capacitor, and
a three-sided gate structure partially surrounding the semiconductor body from three lateral directions including at least two opposite lateral directions, without enclosing a fourth lateral direction,
wherein the three-sided gate structure surrounds a curved sidewall of the semiconductor body; and
a memory controller configured to control the array of memory cells.
13 . A semiconductor device, comprising:
an array of memory cells, each memory cell comprising:
a capacitor; and
a vertical transistor comprising:
a semiconductor body extending in a vertical direction and in contact with the capacitor, and
a three-sided gate structure partially surrounding the semiconductor body from three lateral directions, without enclosing a fourth lateral direction,
wherein the three-sided gate structure surrounds a curved sidewall of the semiconductor body.
14 . The semiconductor device of claim 13 , wherein:
the three-sided gate structures of a row of the vertical transistors along a first lateral direction are connected with each other to form a word line extending along the first lateral direction, and the three lateral directions include at least two opposite lateral directions along the first lateral direction.
15 . The semiconductor device of claim 14 , further comprising:
a plurality of first and second spacers each extending along the first lateral direction between rows of the vertical transistors.
16 . The semiconductor device of claim 15 , wherein:
the plurality of first and second spacers are alternatively arranged along a second lateral direction perpendicular to the first lateral direction.
17 . The semiconductor device of claim 16 , wherein:
the semiconductor body of one vertical transistor comprises a curved sidewall and a flat sidewall.
18 . The semiconductor device of claim 17 , wherein:
each first spacer is located between the curved sidewalls of the semiconductor bodies of two adjacent rows of vertical transistors.
19 . The semiconductor device of claim 17 , wherein:
each second spacer is located between the flat sidewalls of the semiconductor bodies of two adjacent rows of vertical transistors.