Semiconductor memory device having epitaxial layer on the active layer
A semiconductor device includes an active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate, an isolation pattern covering a sidewall of the active pattern, an epitaxial layer on the active pattern and including single crystalline silicon doped with impurities, an impurity region in a portion of the active pattern under the epitaxial layer and including impurities, a conductive filling pattern on the epitaxial layer, a spacer structure on a sidewall of the conductive filling pattern, and a bit line structure on the conductive filling pattern.
1 . A semiconductor device comprising:
an active pattern protruding from an upper surface of a substrate in a vertical direction perpendicular to the upper surface of the substrate;
an isolation pattern covering a sidewall of the active pattern;
an epitaxial layer on the active pattern, the epitaxial layer including single crystalline silicon doped with impurities;
an impurity region in a portion of the active pattern under the epitaxial layer, the impurity region including impurities;
a conductive filling pattern on the epitaxial layer;
a spacer structure directly contacting a sidewall of the conductive filling pattern; and
a bit line structure on the conductive filling pattern,
wherein the isolation pattern directly contacts the upper surface of the substrate, a sidewall of the spacer structure, and a lower surface of the conductive filling pattern.
2 . The semiconductor device according to claim 1 ,
wherein the substrate includes single crystalline silicon, and
wherein the single crystalline silicon included in the epitaxial layer has a crystal plane that is different from a crystal plane of the single crystalline silicon included in the substrate.
3 . The semiconductor device according to claim 2 , wherein the epitaxial layer has a stacking fault.
4 . The semiconductor device according to claim 1 , wherein the impurities included in the impurity region are the same as the impurities included in the epitaxial layer.
5 . The semiconductor device according to claim 1 , wherein a lower surface of the impurity region is lower than or substantially-coplanar with a lower surface of the active pattern.
6 . The semiconductor device according to claim 1 , wherein an interface between the impurity region and the epitaxial layer includes chlorine, bromine, or fluorine.
7 . The semiconductor device according to claim 1 ,
wherein the epitaxial layer is disposed on a central portion of the active pattern, and
wherein an upper surface of the epitaxial layer is lower than an upper surface of each of opposite end portions of the active pattern.
8 . The semiconductor device according to claim 7 , further comprising:
a conductive pad structure on the active pattern and the isolation pattern, the conductive pad structure overlapping at least a portion of the conductive filling pattern in a horizontal direction that is parallel to the upper surface of the substrate.
9 . The semiconductor device according to claim 8 ,
wherein the conductive pad structure contacts each of the opposite end portions of the active pattern, and
wherein the semiconductor device further comprises:
a contact plug structure on the conductive pad structure; and
a capacitor on the contact plug structure.
10 . The semiconductor device according to claim 1 , wherein the epitaxial layer includes a lower portion and an upper portion contacting each other, the lower portion having a width less than a width of the upper portion.
11 . The semiconductor device according to claim 1 ,
wherein the conductive filling pattern includes a metal, and
wherein the semiconductor device further comprises a metal silicide pattern between the epitaxial layer and the conductive filling pattern.
12 . The semiconductor device according to claim 1 , wherein the conductive filling pattern includes a lower portion and an upper portion contacting each other, the lower portion having a width greater than a width of the upper portion.
13 . A semiconductor device comprising:
an active pattern on a substrate;
an epitaxial layer on the active pattern, the epitaxial layer including single crystalline silicon doped with impurities;
an impurity region in a portion of the active pattern under the epitaxial layer, the impurity region including impurities; and
a bit line structure electrically connected to the epitaxial layer,
wherein an interface between the impurity region and the epitaxial layer includes chlorine, bromine, or fluorine, and
wherein the active pattern includes at least one of silicon or germanium.
14 . The semiconductor device according to claim 13 , wherein the epitaxial layer has a stacking fault.
15 . The semiconductor device according to claim 13 , wherein the impurities included in the impurity region are substantially the same as the impurities included in the epitaxial layer.
16 . The semiconductor device according to claim 13 , wherein a lower surface of the impurity region is lower than or coplanar with a lower surface of the active pattern.
17 . The semiconductor device according to claim 13 ,
wherein the epitaxial layer is disposed on a central portion of the active pattern, and
wherein an upper surface of the epitaxial layer is lower than an upper surface of each of opposite end portions of the active pattern.
18 . A semiconductor device comprising:
an active pattern protruding from an upper surface of a substrate in a vertical direction perpendicular to the upper surface of the substrate;
an isolation pattern covering a sidewall of the active pattern;
an epitaxial layer on the active pattern, the epitaxial layer including single crystalline silicon doped with impurities;
an impurity region in a portion of the active pattern under the epitaxial layer, the impurity region including impurities;
a conductive filling pattern on the epitaxial layer;
a lower spacer structure on a sidewall of the conductive filling pattern;
a bit line structure on the conductive filling pattern;
a conductive pad structure on each of opposite end portions of the active pattern, the conductive pad structure overlapping at least a portion of the conductive filling pattern in a horizontal direction parallel to the upper surface of the substrate;
a contact plug structure on the conductive pad structure; and
a capacitor on the contact plug structure,
wherein the isolation pattern directly contacts the upper surface of the substrate, a sidewall of the lower spacer structure, and a lower surface of the conductive filling pattern.
19 . The semiconductor device according to claim 18 , wherein a lower surface of the impurity region is lower than or coplanar with a lower surface of the active pattern.
20 . The semiconductor device according to claim 18 , wherein an interface between the impurity region and the epitaxial layer includes chlorine, bromine, or fluorine.