Semiconductor memory device

1 . A semiconductor memory device comprising:

a peripheral gate structure on a substrate;

bitlines disposed on the peripheral gate structure and extending lengthwise in a first direction;

a protruding insulating pattern including channel trenches, which extend in a second direction that intersects the first direction;

channel structures disposed on the bitlines in the channel trenches and including a metal oxide;

first wordlines disposed on the channel structures and extending lengthwise in the second direction;

second wordlines disposed on the channel structures, extending lengthwise in the second direction, and spaced apart from the first wordlines in the first direction;

landing pads disposed on the channel structures and connected to the channel structures;

pad separation patterns disposed on the protruding insulating pattern and separating the landing pads;

first passage patterns connected to the protruding insulating pattern through the pad separation patterns and formed of an oxide-based insulating material; and

data storage patterns disposed on the landing pads.

2 . The semiconductor memory device of claim 1 , further comprising:

gate separation patterns disposed between the first wordlines and the second wordlines and filling the channel trenches; and

second passage patterns connected to the gate separation patterns through the pad separation patterns and formed of an oxide-based insulating material.

3 . The semiconductor memory device of claim 2 ,

wherein the gate separation patterns include gate separation filling films and gate separation capping films, which are disposed on the gate separation filling films, and

wherein the second passage patterns are connected to the gate separation filling films through the gate separation capping films.

4 . The semiconductor memory device of claim 1 ,

wherein the data storage patterns include lower electrodes on the landing pads, a capacitor dielectric film on the lower electrodes, and an upper electrode on the capacitor dielectric film, and

wherein the first passage patterns are in contact with the capacitor dielectric film.

5 . The semiconductor memory device of claim 1 ,

wherein each of the first wordlines includes first portions and second portions, which are alternately arranged in the second direction, and

wherein a width, in the first direction, of the first portions of the first wordlines is less than a width, in the first direction, of the second portions of the first wordlines.

6 . The semiconductor memory device of claim 5 , wherein the channel structures is disposed between second portions of the first wordlines adjacent in the second direction.

7 . The semiconductor memory device of claim 1 , further comprising:

a gate insulating film disposed between the channel structures and the first wordlines,

wherein a height from the bitlines to an uppermost part of the gate insulating film is greater than a height from the bitlines to uppermost parts of the first wordlines.

8 . The semiconductor memory device of claim 1 , further comprising:

a gate insulating film disposed between the channel structures and the first wordlines,

wherein each of the channel structures includes a horizontal portion, which extends along a bottom surface of the channel trenches, and vertical portions, which protrude from the horizontal portion, and

wherein a height from the bitlines to an uppermost part of the gate insulating film is greater than a height from the bitlines to uppermost parts of the vertical portions of the channel structures.

9 . A semiconductor memory device comprising:

a substrate including a cell array region and a peripheral circuit region;

a peripheral gate structure on the substrate;

lower peripheral lines disposed on the peripheral gate structure and connected to the peripheral gate structure;

dummy peripheral lines disposed on the peripheral gate structure and not connected to the peripheral gate structure;

bitlines disposed on the lower peripheral lines and the dummy peripheral lines and extending lengthwise in a first direction;

bitline plugs connecting the bitlines and the lower peripheral lines in the peripheral circuit region;

dummy bitline plugs connecting the bitlines and the dummy peripheral lines in the peripheral circuit region;

a protruding insulating pattern including channel trenches, which extend in a second direction that intersects the first direction, the channel trenches being disposed on the cell array region of the substrate;

channel structures disposed on the bitlines in the channel trenches and including a metal oxide;

first wordlines disposed on the channel structures and extending lengthwise in the second direction;

second wordlines disposed on the channel structures, extending lengthwise in the second direction, and spaced apart from the first wordlines in the first direction;

landing pads disposed on the channel structures and connected to the channel structures;

pad separation patterns disposed on the protruding insulating pattern and separating the landing pads; and

capacitors disposed on the landing pads.

10 . The semiconductor memory device of claim 9 , further comprising:

passage patterns connected to the protruding insulating pattern penetrating the pad separation patterns and formed of an oxide.

11 . The semiconductor memory device of claim 9 , further comprising:

a gate insulating film disposed between the channel structures and the first wordlines,

wherein each of the channel structures includes a horizontal portion, which extends along a bottom surface of one of the channel trenches, and vertical portions, which protrude from the horizontal portion, and

wherein a height from the bitlines to an uppermost part of the gate insulating film is greater than a height from the bitlines to uppermost parts of the vertical portions of the channel structures.

12 . The semiconductor memory device of claim 9 ,

wherein each of the first wordlines includes first portions and second portions, which are alternately arranged in the second direction,

wherein a width in the first direction of the first portions of the first wordlines is less than a width, in the first direction, of the second portions of each of the first wordlines, and

wherein each of the channel structures is disposed between second portions of the first wordlines adjacent in the second direction.