Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes forming a buffer layer on a substrate including active regions and word lines, sequentially stacking a first conductive layer and a first insulating layer, forming bit line structure main parts such that each bit line main part is in contact with one or more of the active regions through a plurality of first contacts, by etching the first insulating layer and the first conductive layer, stacking first spacers, forming bit line structure expansions by etching the first spacers, the first insulating layer, and the first conductive layer, and forming second contacts such that the second contacts are in contact with the active regions, respectively. The bit line structure expansions are connected to the bit line structure main parts, respectively, and are wider than the bit line structure main parts as viewed in a plan view.
1 . A method of manufacturing a semiconductor device, the method comprising:
forming a buffer layer on a substrate, the substrate including a plurality of active regions and a plurality of word lines;
sequentially stacking a first conductive layer and a first insulating layer in a first direction perpendicular to an upper surface of the substrate;
forming a plurality of bit line structure main parts such that each of the plurality of bit line structure main parts is in contact with one or more of the active regions through a plurality of first contacts, by etching the first insulating layer and the first conductive layer;
stacking first spacers;
forming a plurality of bit line structure expansions by etching the first spacers, the first insulating layer, and the first conductive layer; and
forming a plurality of second contacts such that the second contacts are in contact with the plurality of active regions, respectively, wherein
each of the plurality of active regions includes a first part and a second part located on opposite sides with respect to a word line,
each of the plurality of bit line structure main parts is in contact with one or more of the first parts of the active regions and the first contacts,
each of the plurality of second contacts is in contact with the second part of one of the active regions, and
the plurality of bit line structure expansions are connected to the plurality of bit line structure main parts, respectively, and are wider than the plurality of bit line structure main parts, respectively, as viewed in a plan view.
2 . The method according to claim 1 , wherein
forming the plurality of bit line structure main parts includes forming a plurality of main-part separation grooves, each of the plurality of main-part separation grooves separating two adjacent bit line structure main parts of the plurality of the bit line structure main parts,
forming the plurality of bit line structure expansions includes forming a plurality of expansion separation grooves, each of the plurality of expansion separation grooves separating two adjacent bit line structure expansions of the plurality of bit line structure expansions, and
each of the plurality of expansion separation grooves laterally overlaps two adjacent main-part separation grooves of the plurality of main-part separation grooves.
3 . The method according to claim 2 , wherein
the two adjacent main-part separation grooves are different from each other in their lengths.
4 . The method according to claim 2 , wherein
forming the plurality of expansion separation grooves includes removing parts of the buffer layer exposed by the plurality of expansion separation grooves.
5 . The method according to claim 4 , further comprising:
after removing the parts of the buffer layer exposed from the plurality of expansion separation grooves, stacking second spacers.
6 . The method according to claim 5 , further comprising:
exposing the substrate by removing at least parts of the second spacers, the first spacers, and parts of the buffer layer on bottom surfaces of the plurality of main-part separation grooves and bottom surfaces of the plurality of expansion separation grooves.
7 . The method according to claim 6 , wherein
exposing the substrate includes etching some of upper parts of the exposed parts of the substrate.
8 . The method according to claim 6 , further comprising:
after exposing the substrate, stacking third spacers on the second spacers.
9 . The method according to claim 8 , further comprising:
exposing second parts of the substrate by removing at least parts of the third spacers on the bottom surfaces of the plurality of main-part separation grooves.
10 . The method according to claim 9 , wherein
exposing the second parts of the substrate includes:
forming a photosensitive film on the plurality of bit line structure expansions and the plurality of expansion separation grooves; and
removing parts of the third spacers on the plurality of bit line structure main parts and parts of the third spacers on the bottom surfaces of the plurality of main-part separation grooves, using the photosensitive film as a mask.
11 . The method according to claim 9 , wherein
forming the plurality of second contacts includes:
stacking a second conductive layer on the first conductive layer after exposing the second parts of the substrate; and
forming the plurality of second contacts by etching the second conductive layer.
12 . The method according to claim 11 , wherein
forming the plurality of second contacts by etching the second conductive layer includes:
forming trenches separating the second conductive layer; and
forming a plurality of partitions by filling the trenches with an insulating material.
13 . The method according to claim 12 , wherein
forming the plurality of second contacts by etching the second conductive layer further includes dividing the second conductive layer by etching an upper surface of the second conductive layer such that the upper surface of the second conductive layer is coplanar with upper surfaces of the plurality of bit line structure main parts, before forming the trenches, and
the trenches divide the second conductive layer that was separated by the trenches.
14 . The method according to claim 9 , further comprising:
filling the plurality of expansion separation grooves with an insulating material.