Semiconductor structure using lining layer to prevent electrical connection between contacts and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor structure including a dielectric layer stack, an isolation structure, a lining layer and a contact. The isolation structure is in contact with a sidewall of the dielectric layer stack, and the sidewall of the dielectric layer stack and a sidewall of the isolation structure define a sharp corner. The lining layer is at the sharp corner, and a sidewall of the lining layer, the sidewall of the dielectric layer stack and the sidewall of the isolation structure define a round corner. The contact is in contact with the sidewall of the dielectric layer stack, the sidewall of the isolation structure and the sidewall of the lining layer.
1 . A semiconductor structure, comprising:
a dielectric layer stack;
an isolation structure in contact with a sidewall of the dielectric layer stack, wherein the sidewall of the dielectric layer stack and a sidewall of the isolation structure define a sharp corner in a top view;
a lining layer at the sharp corner, wherein a sidewall of the lining layer, the sidewall of the dielectric layer stack and the sidewall of the isolation structure define a round corner in the top view; and
a contact in contact with the sidewall of the dielectric layer stack, the sidewall of the isolation structure and the sidewall of the lining layer.
2 . The semiconductor structure of claim 1 , wherein a contour of the contact has a round corner defined by the sidewall of the dielectric layer stack, the sidewall of the isolation structure and the sidewall of the lining layer.
3 . The semiconductor structure of claim 1 , wherein an interface is between the lining layer and the isolation structure.
4 . The semiconductor structure of claim 1 , wherein the dielectric layer stack comprises a bottom portion under and in contact the lining layer.
5 . The semiconductor structure of claim 1 , further comprising a bitline, wherein the dielectric layer stack has a first portion between the bitline and the contact and a second portion between the bitline and the isolation structure.
6 . The semiconductor structure of claim 5 , wherein the dielectric layer stack comprises a first nitride layer, an oxide layer and a second nitride layer arranged from the bitline to the contact.
7 . The semiconductor structure of claim 1 , further comprising an active area under the contact and in contact with the contact.
8 . A semiconductor structure, comprising:
a dielectric layer stack;
an isolation structure in contact with a sidewall of the dielectric layer stack, wherein the sidewall of the dielectric layer stack and a sidewall of the isolation structure defines a sharp corner in a top view;
a contact in contact with the sidewall of the dielectric layer stack and the sidewall of the isolation structure, wherein the contact has a round corner in the top view; and
a lining layer between the contact, the isolation structure and the dielectric layer stack.
9 . The semiconductor structure of claim 8 , wherein the round corner of the contact is adjacent to the sharp corner defined by the sidewall of the dielectric layer stack and the sidewall of the isolation structure.
10 . The semiconductor structure of claim 8 , wherein the lining layer has a first concave surface in contact with the isolation structure and a second concave surface in contact with the contact.
11 . The semiconductor structure of claim 8 , wherein compositions of the lining layer and the isolation structure are different.
12 . The semiconductor structure of claim 8 , wherein a minimum width of the contact parallel to the sidewall of the dielectric layer stack is at the sidewall of the dielectric layer stack.
13 . The semiconductor structure of claim 8 , wherein a maximum width of the contact parallel to the sidewall of the dielectric layer stack is substantially at the center of the contact.
14 . The semiconductor structure of claim 8 , wherein the dielectric layer stack comprises a bottom portion under and in contact the lining layer, and a sidewall of the lining layer is aligned with a sidewall of the bottom portion of the dielectric layer stack.