Asymmetric single-channel floating gate memristor
A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source/drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source/drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and/or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program/erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.
1 . A two-terminal memristor comprising:
a substrate having an upper surface and including a drain region and a source region separated by a channel region;
a gate oxide layer disposed on the upper surface;
a single-piece, integral floating polycrystalline silicon structure disposed on the gate oxide layer and including a first poly portion disposed over the drain region, a second poly portion disposed over the source region and a third poly portion connected between the first and second poly portions and extending over the channel region; and
an asymmetric channel doping pattern including at least two implants asymmetrically disposed in the channel region between the drain region and the source region,
wherein the single-piece, integral floating polycrystalline silicon structure, the drain region and the source region are configured to generate asymmetric source/drain-to-gate coupling such that a gate-to-drain capacitance generated between the first poly portion and the drain region is greater than a gate-to-source capacitance generated between the second poly portion and the source region, and
wherein said at least two implants comprises at least one N-type dopant implant and at least one P-type dopant implant.
2 . The two-terminal memristor of claim 1 , wherein said asymmetric channel doping pattern comprises at least one of (i) a single P-type implant disposed adjacent to the drain region and (ii) a single N-type implant disposed adjacent to the source region.
3 . The two-terminal memristor of claim 1 , wherein said single-piece, integral floating polycrystalline silicon gate structure comprises the only polycrystalline silicon structure of said two-terminal memristor.
4 . The two-terminal memristor of claim 3 , wherein said single-piece, integral floating polycrystalline silicon gate structure comprises a c-shaped polycrystalline silicon structure including first and second arms extending in parallel from a base, wherein the first and second arms extend over the drain region and a portion of the base extends over the source region.
5 . The two-terminal memristor of claim 1 , wherein said at least two implants forming the asymmetric channel doping pattern comprises both an N-type implant and a P-type implant.
6 . The two-terminal memristor of claim 5 , wherein the P-type implant is disposed adjacent to the drain region and the N-type implant is disposed adjacent to the source region.
7 . The two-terminal memristor of claim 5 , wherein the N-type implant abuts the drain region and the P-type implant abuts the N-type implant.
8 . The two-terminal memristor of claim 7 , further comprising a second N-type implant abutting the source region.
9 . The two-terminal memristor of claim 5 , wherein the N-type implant is disposed adjacent to the drain region and the P-type implant is disposed adjacent to the source region.
10 . The two-terminal memristor of claim 1 ,
wherein both the drain region and the source comprise N+ doped regions disposed in a p-type silicon substrate, and
wherein the two-terminal memristor further comprises a diode is at least partially disposed in an N-well region that is formed in the p-type silicon substrate, said N-well region abutting the N+ drain region.
11 . The two-terminal memristor of claim 10 , wherein the diode comprises a Schottky diode including a silicide structure disposed in contact with said N-well region by way of an upper surface of said p-type silicon substrate.
12 . The two-terminal memristor of claim 10 , wherein the diode comprises a Schottky diode including a junction formed between a metal contact structure disposed in contact with said N-well region by way of an upper surface of said p-type silicon substrate.
13 . The two-terminal memristor of claim 11 , wherein the diode comprises a P+ diffusion region disposed in the N-well region and connected to a first terminal of the two-terminal memristor.
14 . A memory circuit comprising a plurality of two-terminal memristors fabricated on a semiconductor substrate and disposed in a cross-point array, each said memristor having a first terminal connected to an associated first line and a second terminal connected to an associated second line, wherein said each memristor comprises:
a drain region and a source region formed in the substrate and separated by a channel region;
a single-piece, integral floating polycrystalline silicon structure including a first poly portion disposed over the drain region, a second poly portion disposed over the source region and a third poly portion connected between the first and second poly portions and extending over the channel region; and
an asymmetric channel doping pattern including at least two implants asymmetrically disposed in the channel region between the drain region and the source region,
wherein the single-piece, integral floating polycrystalline silicon structure, the drain region and the source region are configured to generate asymmetric source/drain-to-gate coupling such that a gate-to-drain capacitance generated between the first poly portion and the drain region is greater than a gate-to-source capacitance generated between the second poly portion and the source region, and
wherein said at least two implants comprises at least one N-type dopant implant and at least one P-type dopant implant.
15 . The memory circuit according to claim 14 , further comprising a control circuit configured to apply a positive programming voltage to the associated first line of said each memristor while coupling the associated second line to ground during a program operation period, thereby generating a channel hot electron (CHE) injection mechanism that causes the injection of electrons into said single-piece, integral floating polycrystalline silicon gate structure by way of said second poly portion, whereby the resulting programmed charge stored on said single-piece, integral floating polycrystalline silicon gate structure increases the threshold voltage of said each memristor.
16 . The memory circuit according to claim 14 , further comprising a control circuit configured to apply a positive erase voltage to the associated second line of said each memristor while coupling the associated first line to ground during an erase operation period, thereby generating a band-to-band tunneling mechanism that causes the injection of holes into said single-piece, integral floating polycrystalline silicon gate structure by way of said second poly portion), whereby an erased charge stored on said single-piece, integral floating polycrystalline silicon gate structure decreases the threshold voltage of said each memristor.
17 . The memory circuit according to claim 14 , further comprising a control circuit configured to apply a first positive readout voltage to the associated first line of said each memristor and to apply a second positive readout voltage to the associated second line, said first readout voltage being higher than said second readout voltage, said control circuit also being configured to measure the resulting read current passed through said each memristor onto the associated second line during a readout operation period.
18 . A neuromorphic circuit comprising a plurality of two-terminal memristors fabricated on a semiconductor substrate, each said memristor comprising:
a drain region and a source region formed in the substrate and separated by a channel region;
a single-piece, integral floating polycrystalline silicon structure including a first poly portion disposed over the drain region, a second poly portion disposed over the source region and a third poly portion connected between the first and second poly portions and extending over the channel region; and
an asymmetric channel doping pattern including at least two implants asymmetrically disposed in the channel region between the drain region and the source region,
wherein the single-piece, integral floating polycrystalline silicon structure, the drain region and the source region are configured to generate asymmetric source/drain-to-gate coupling such that a gate-to-drain capacitance generated between the first poly portion and the drain region is greater than a gate-to-source capacitance generated between the second poly portion and the source region, and
wherein said at least two implants comprises at least one N-type dopant implant and at least one P-type dopant implant.
19 . The neuromorphic circuit of claim 18 , further comprising a control circuit configured to:
apply a positive programming voltage to the first terminal of said each memristor while coupling the second terminal of said each memristor to ground during a program operation period such that electrons are injected into said single-piece, integral floating polycrystalline silicon gate structure, and
apply a positive erase voltage to the associated second terminal of said each memristor while coupling the first terminal of said each memristor to ground during an erase operation period such that holes are injected into said single-piece, integral floating polycrystalline silicon gate structure.