Bit-erasable embedded select in trench memory (ESTM)
In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.
1 . A memory cell comprising:
a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type;
a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type;
a first wall in contact with the second and fourth doped wells, the first wall comprising a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells; and
a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.
2 . The memory cell according to claim 1 , wherein the first conductivity type is a N type and the second conductivity type is a P type.
3 . The memory cell according to claim 1 , wherein the second and fourth doped wells are separated by the first wall.
4 . The memory cell according to claim 3 , wherein the stack of layers covers the first wall.
5 . The memory cell according to claim 3 , wherein the second insulating layer is in contact with the first wall.
6 . The memory cell according to claim 1 , further comprising a third semiconductor layer located below the second and fourth doped wells and the first wall, wherein the third semiconductor layer is separated from the fourth doped well by a doped semiconductor well of the second conductivity type.
7 . A method for controlling the memory cell according to claim 6 , the method comprising:
setting the second, third, and fourth doped wells and the third semiconductor layer to a first reference potential;
setting the first doped well to a second positive potential, the second positive potential being greater than the first reference potential;
setting the second semiconductor layer to a third positive potential, the third positive potential being greater than the second positive potential; and
setting the first wall to a fourth potential equal to a threshold voltage of a transistor comprising the first, second, and third doped wells and the stack of layers,
wherein controlling comprises programming.
8 . A method for controlling the memory cell according to claim 6 , the method comprising:
setting the second, third, and fourth doped wells and the second semiconductor layer and the third semiconductor layer to a fifth reference potential;
setting the first doped well to a sixth positive potential, the sixth positive potential being greater than the fifth reference potential; and
setting the first wall to a seventh positive potential, the seventh positive potential being greater than the sixth positive potential,
wherein controlling comprises reading.
9 . The method according to claim 8 , wherein the fifth reference potential is ground, the sixth positive potential is substantially equal to 0.7 V, and the seventh positive potential is substantially equal to 3 V.
10 . A method for controlling the memory cell according to claim 6 , the method comprising:
setting the first, second and third doped wells and the third semiconductor layer to an eighth reference potential;
setting the fourth doped well to a ninth potential, the ninth potential being smaller than the eighth reference potential;
setting the second semiconductor layer to a tenth potential, the tenth potential being smaller than the ninth potential; and
setting the first wall to an eleventh potential equal to a threshold voltage of a transistor comprising the second, third, and fourth doped wells and the stack of layers,
wherein controlling comprises erasing.
11 . The method according to claim 10 , wherein the eighth reference potential is ground, the ninth potential is substantially equal to −5 V, the tenth potential is substantially equal to −10 V, and the eleventh potential is in a range from −1.5 V to −0.5 V.
12 . The method according to claim 10 , wherein the eighth reference potential is substantially equal to 10 V, the ninth potential is substantially equal to 5 V, the tenth potential is ground, and the eleventh potential is in a range from 5 V to 15 V.
13 . The method according to claim 10 , wherein the eighth reference potential is substantially equal to 5 V, the ninth potential is ground, the tenth potential is substantially equal to −5 V, and the eleventh potential is in a range from 0 V to 15 V.
14 . A method for manufacturing the memory cell according to claim 6 , the method comprising:
a. forming the third semiconductor layer by implanting layer dopants into a semiconductor substrate;
b. forming the second doped well by implanting second dopants into the semiconductor substrate;
c. forming the fourth doped well by implanting fourth dopants into the semiconductor substrate;
d. forming the first wall between the second and third doped wells;
e. forming the stack of layers on a portion of the second and fourth doped wells and on the first wall;
f. forming the first doped well by implanting first dopants into the second doped well; and
g. forming the third doped well by implanting dopants into the fourth doped well.
15 . The method according to claim 14 , wherein a first memory cell is formed by a, b, c, d, e, f, and g, and wherein a second memory cell is formed by a, b, d, e and f.
16 . The method according to claim 14 , wherein a first memory cell is formed by a, b, c, d, e, f, wherein a gate of a transistor is formed by e, and wherein drain and source regions are formed by f or g.
17 . The method according to claim 7 , wherein the first reference potential is ground, the second positive potential is substantially equal to 5 V, the third positive potential is substantially equal to 12 V, and the fourth potential is in a range from 0.5 V to 1.5 V.
18 . The memory cell according to claim 1 , wherein the second and fourth doped wells are separated by a second insulating wall.
19 . The memory cell according to claim 18 , wherein the stack of layers covers the second insulating wall.
20 . A memory comprising:
an array of memory cells according to claim 1 ,
wherein each column of the array comprises a respective second semiconductor layer and a respective first wall common to cells of a column.