Pillar memory device having a hollow central region and method for manufacturing the same
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include memory strings with a conductor channel shell and a low dielectric constant central region. In one example, memory devices, systems and methods include memory strings with a conductor channel shell and a hollow central region.
1 . A memory string, comprising:
a central pillar, including a conductor channel shell, the conductor channel shell having a hollow central region that includes an oxide having a dielectric constant less than 3;
a plurality of gates along a length of the central pillar;
a source line coupled to a first end of the conductor channel shell; and
a data line coupled to a second end of the conductor channel shell.
2 . The memory string of claim 1 , wherein the conductor channel shell includes polysilicon.
3 . The memory string of claim 1 , further including a nitride storage layer between the plurality of gates and the conductor channel shell.
4 . The memory string of claim 1 , wherein the plurality of gates includes metal gates.
5 . The memory string of claim 1 , wherein the plurality of gates includes polysilicon gates.
6 . The memory string of claim 1 , wherein the plurality of gates includes floating gates.
7 . An electronic device, comprising:
an array of vertical memory cell strings, including at least one memory cell string that includes;
a central pillar, including a conductor channel shell, the conductor channel shell having a central region that includes an oxide having a dielectric constant less than 3;
a plurality of gates along a length of the central pillar;
a number of source lines coupled to first ends of conductor channel shells in the array;
a number of bit lines coupled to second ends of conductor channel shells in the array; and
a number of wordlines coupled to the plurality of gates in the array.
8 . The electronic device of claim 7 , further including a processing device coupled to the array of vertical memory cell strings.
9 . The electronic device of claim 7 , further including a network interface device coupled to the array of vertical memory cell strings.
10 . The electronic device of claim 7 , wherein the conductor channel shell includes polysilicon.
11 . The electronic device of claim 7 , further including a nitride storage layer between the plurality of gates and the conductor channel shell.
12 . A method of forming a memory device, comprising:
forming a plurality of layers on a semiconductor substrate, the layers including conducting layers and dielectric layers;
forming a vertical hole through at least a portion of the plurality of layers;
forming a central pillar within the vertical hole, including;
forming a first dielectric layer within the vertical hole, followed by a storage layer over the first dielectric layer;
forming a second dielectric layer over the storage layer, followed by a conducting layer wherein the conducting layer forms a conductor channel shell, the conductor channel shell having a hollow central region; and
filling the hollow central region with an oxide having a dielectric constant less than 3.
13 . The method of claim 12 , wherein forming the vertical hole includes etching a vertical hole.