Nonvolatile memory device with integrated backgate and method of manufacturing
Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including a plurality of interlayer insulating layers and a plurality of conductive layers that are alternately stacked, wherein a top-most conductive layer, among the plurality of conductive layers, corresponds to a backgate line and the rest of the plurality of conductive layers correspond to word lines, and a vertical channel structure passing through the gate stacked body. A first part of the vertical channel structure passing through the plurality of interlayer insulating layers and the plurality of conductive layers corresponding to the word lines has a circular structure in a plan view, and a second part of the vertical channel structure passing through the conductive layer corresponding to the backgate line has a pair of semicircular structures that are separated from each other in a plan view.
1 . A semiconductor memory device comprising:
a gate stacked body comprising a plurality of interlayer insulating layers and a plurality of conductive layers that are alternately stacked, wherein a top-most conductive layer, among the plurality of conductive layers, corresponds to a backgate line and the rest of the plurality of conductive layers correspond to word lines; and
a vertical channel structure passing through the gate stacked body,
wherein a first part of the vertical channel structure passing through the plurality of interlayer insulating layers and the plurality of conductive layers corresponding to word lines has a circular structure in a plan view, and a second part of the vertical channel structure passing through the conductive layer corresponding to the backgate line has a pair of semicircular structures that are separated from each other in a plan view;
wherein, a portion of the conductive layer corresponding to the backgate line is disposed between the pair of semicircular structures of the second part of the vertical channel structure.
2 . The semiconductor memory device according to claim 1 , wherein the first part of the vertical channel structure comprises:
a vertically extending backgate;
a backgate insulating layer enclosing a sidewall of the backgate;
a channel layer enclosing a sidewall of the backgate insulating layer; and
a memory layer enclosing a sidewall of the channel layer.
3 . The semiconductor memory device according to claim 2 , wherein:
the second part of the vertical channel structure comprises a first portion and a second portion, each having a semicircular cross-section, and
each of the first and second portions comprises:
a first gap insulating layer having a curved sidewall and a linear sidewall;
the backgate insulating layer enclosing the curved sidewall of the first gap insulating layer;
the channel layer enclosing a curved sidewall of the backgate insulating layer;
the memory layer enclosing a curved sidewall of the channel layer; and
a second gap insulating layer disposed between two ends of the channel layer and the conductive layer corresponding to the backgate line.
4 . The semiconductor memory device according to claim 3 , wherein the conductive layer corresponding to the backgate line is directly connected to an upper surface of the backgate between the first portion and the second portion.
5 . The semiconductor memory device according to claim 3 , further comprising:
a capping layer disposed on top of the first and second portions.
6 . The semiconductor memory device according to claim 5 , wherein the first gap insulating layer is disposed between the capping layer and the backgate.
7 . The semiconductor memory device according to claim 3 , wherein the conductive layer corresponding to the backgate line is disposed between the first gap insulating layer of the first portion and the first gap insulating layer of the second portion.
8 . The semiconductor memory device according to claim 3 , wherein the second part of the vertical channel structure is separated into the first portion and the second portion by a line-shaped trench.
9 . The semiconductor memory device according to claim 8 , wherein a lower surface of the line-shaped trench contacts an upper surface of the backgate.
10 . The semiconductor memory device according to claim 8 , wherein the conductive layer corresponding to the backgate line is disposed on a lower surface of the line-shaped trench.