Microelectronic devices with increased grain size

1 . A method of forming a microelectronic device, the method comprising:

forming conductive interconnect structures vertically extending through insulative material to conductive contact structures coupled to pillar structures comprising semiconductive material;

forming a metal silicide material on the conductive interconnect structures and the insulative material;

forming a conductive material on the metal silicide material;

forming a dielectric material over the conductive material;

forming openings vertically extending through the dielectric material, the conductive material, and the metal silicide material and into the insulative material to form dielectric structures from the dielectric material, conductive line structures from the conductive material, and metal silicide structures from the metal silicide material; and

forming additional insulative material to extend over the dielectric structures and partially fill the openings to form air gaps underlying the additional insulative material, each of the air gaps vertically overlapping and horizontally interposed between each of a horizontally neighboring pair of the dielectric structures, a horizontally neighboring pair of the conductive line structures, and a horizontally neighboring pair of the metal silicide structures.

2 . The method of claim 1 , further comprising:

forming the metal silicide material to comprise tungsten silicide; and

forming the conductive material to comprise tungsten.

3 . The method of claim 1 , wherein forming a conductive material on the metal silicide material comprises forming the conductive material to exhibit a tensile stress greater than about 1000 MPa.

4 . The method of claim 1 , wherein forming a conductive material on the metal silicide material comprises forming the conductive material to have a mean grain size within a range of from about 100 nm to about 800 nm.

5 . The method of claim 1 , wherein forming a metal silicide material comprises forming the metal silicide material to have a vertical thickness within a range of from about 10 Å to about 25 Å.

6 . The method of claim 1 , wherein forming a metal silicide material comprises forming the metal silicide material to be substantially amorphous.

7 . A microelectronic device, comprising:

pillar structures comprising semiconductor material;

insulative material overlying the pillar structures;

conductive interconnect structures extending through isolation material and in electrical communication with the pillar structures;

metal silicide structures on the insulative material and the conductive interconnect structures;

conductive line structures on the metal silicide structures;

dielectric structures over the conductive line structures;

additional insulative material over the dielectric structures and horizontally extending across and between the dielectric structures; and

air gaps underlying the additional insulative material, each of the air gaps vertically overlapping and horizontally interposed between each of a horizontally neighboring pair of the dielectric structures, a horizontally neighboring pair of the conductive line structures, and a horizontally neighboring pair of the metal silicide structures.

8 . The microelectronic device of claim 7 , wherein:

the metal silicide structures comprise tungsten silicide; and

the conductive line structures comprise tungsten.

9 . The microelectronic device of claim 7 , wherein the metal silicide structures comprise one or more of tungsten silicide, tantalum silicide, titanium silicide, nickel silicide, and copper silicide.

10 . The microelectronic device of claim 7 , wherein the metal silicide structures are substantially homogeneous.

11 . The microelectronic device of claim 7 , wherein the conductive line structures individually have a mean grain size within a range of from about 100 nm to about 800 nm.

12 . A microelectronic device, comprising:

pillar structures comprising semiconductor material;

insulative material overlying the pillar structures;

conductive interconnect structures extending through isolation material and in electrical communication with the pillar structures;

metal silicide structures on the insulative material and the conductive interconnect structures;

conductive line structures on the metal silicide structures;

dielectric structures over the conductive line structures;

additional insulative material over the dielectric structures and horizontally extending across and between the dielectric structures;

a stack structure underlying the insulative material and comprising tiers each comprising a conductive structure and an insulative structure vertically neighboring the conductive structure, the pillar structures vertically extending through the stack structure and into the insulative material; and

conductive plug structures within the insulative material, the conductive plug structures vertically interposed between and in electrical communication with the pillar structures and the interconnect structures.

13 . A memory device, comprising:

a stack structure including tiers each comprising conductive material vertically adjacent insulative material;

isolation material vertically overlying the stack structure;

pillar structures comprising semiconductor material vertically extending through the stack structure and into the isolation material, intersections of the pillar structures and the conductive material of the tiers of the stack structure forming vertically extending strings of memory cells;

conductive interconnect structures within the isolation material and vertically overlying and in electrical communication with the pillar structures;

metal silicide structures on the isolation material and the conductive interconnect structures;

digit line structures on the metal silicide structures and individually having a mean grain size greater than or equal to about 100 nm; and

dielectric line structures on the digit line structures;

additional isolation material vertically on and horizontally extending across and between the dielectric line structures; and

air gaps vertically underlying the additional isolation material and individually horizontally interposed between each of two of the dielectric line structures horizontally neighboring one another, two of the digit line structures horizontally neighboring one another, and two of the metal silicide structures horizontally neighboring one another.

14 . The memory device of claim 13 , wherein the mean grain size of the digit line structures is within a range of from about 100 nm to about 800 nm.

15 . The memory device of claim 13 , wherein lower vertical boundaries of the air gaps are positioned between upper vertical boundaries and lower vertical boundaries of the conductive interconnect structures.