3D semiconductor devices and structures with logic and memory, and a semiconductor die
A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.
1 . A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors,
wherein said first level comprises a first metal layer, a second metal layer, and a third metal layer, and
wherein connection of said plurality of first transistors comprises said first metal layer, and/or said second metal layer, and/or said third metal layer;
a plurality of second transistors disposed atop said first level;
a plurality of third transistors disposed atop said plurality of second transistors;
a fourth metal layer disposed atop said plurality of third transistors;
a memory array comprising word-lines,
wherein said memory array comprises at least four memory mini-arrays,
wherein each of said memory mini-arrays comprises at least four rows by four columns of memory cells,
wherein at least one of said plurality of second transistors comprises a metal gate, and
wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors;
a connection path from said fourth metal to said third metal,
wherein said connection path comprises a via disposed through said memory array; and
a semiconductor die disposed atop said first level,
wherein said semiconductor die comprises said plurality of second transistors,
wherein said semiconductor die comprises at least one alignment mark, and
wherein at least one of said at least one alignment mark is positioned toward an edge of said semiconductor die.
2 . The 3D semiconductor device according to claim 1 ,
wherein said memory control circuit is configured to control each of said four memory mini-arrays independently.
3 . The 3D semiconductor device according to claim 1 ,
wherein said memory control circuit comprises a plurality of voltage regulators.
4 . The 3D semiconductor device according to claim 1 ,
wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”).
5 . The 3D semiconductor device according to claim 1 ,
wherein said memory control circuit comprises at least one cache memory unit.
6 . The 3D semiconductor device according to claim 1 , further comprising:
an upper level disposed atop said fourth metal layer,
wherein said upper level comprises a mono-crystalline silicon layer.
7 . The 3D semiconductor device according to claim 1 ,
wherein said memory control circuit comprises at least one power down control circuit.
8 . A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors,
wherein said first level comprises a first metal layer, a second metal layer, and a third metal layer, and
wherein connection of said plurality of first transistors comprises said first metal layer, and/or said second metal layer, and/or said third metal layer;
a plurality of second transistors disposed atop said first level;
a plurality of third transistors disposed atop said plurality of second transistors;
a fourth metal layer disposed atop said plurality of third transistors;
a memory array comprising word-lines,
wherein said memory array comprises at least four memory mini-arrays,
wherein each of said memory mini-arrays comprises at least four rows by four columns of memory cells,
wherein at least one of said plurality of second transistors comprises a metal gate, and
wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors;
a connection path from said fourth metal to said third metal,
wherein said connection path comprises a via disposed through said memory array, and
wherein said memory control circuit comprises at least one SRAM cache memory circuit; and
a semiconductor die disposed atop said first level,
wherein said semiconductor die comprises said plurality of second transistors,
wherein said semiconductor die comprises at least one alignment mark, and
wherein at least one of said at least one alignment mark is positioned toward an edge of said semiconductor die.
9 . The 3D semiconductor device according to claim 8 ,
wherein said memory control circuit is configured to control each of said at least four memory mini-arrays independently.
10 . The 3D semiconductor device according to claim 8 ,
wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.
11 . The 3D semiconductor device according to claim 8 ,
wherein said first level comprises at least one in-out interface control circuit.
12 . The 3D semiconductor device according to claim 8 ,
wherein said first level comprises at least one differential read circuit.
13 . The 3D semiconductor device according to claim 8 , further comprising:
an upper level disposed atop said fourth metal layer,
wherein said upper level comprises a mono-crystalline silicon layer.
14 . The 3D semiconductor device according to claim 8 , further comprising:
a second connection path between said fourth metal and said second metal,
wherein said second connection path comprises a via disposed through said memory array.
15 . A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors,
wherein said first level comprises a first metal layer, a second metal layer, and third metal layer, and
wherein connection of said plurality of first transistors comprises said first metal layer, and/or said second metal layer, and/or said third metal layer;
a plurality of second transistors disposed atop said first level;
a plurality of third transistors disposed atop said plurality of second transistors;
a fourth metal layer disposed atop said plurality of third transistors;
a memory array comprising word-lines,
wherein said memory array comprises at least four memory mini-arrays,
wherein each of said memory mini-arrays comprises at least four rows by four columns of memory cells,
wherein at least one of said plurality of second transistors comprises a metal gate, and
wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors;
a connection path from said fourth metal to said third metal,
wherein said connection path comprises a via disposed through said memory array,
wherein said memory control circuit comprises a plurality of antifuse elements; and
a semiconductor die disposed atop said first level,
wherein said semiconductor die comprises said plurality of second transistors, and
wherein said semiconductor die comprises at least one alignment mark,
wherein at least one of said at least one alignment mark is positioned toward an edge of said semiconductor die.
16 . The 3D semiconductor device according to claim 15 ,
wherein said memory control circuit is configured to control each of said at least four memory mini-arrays independently.
17 . The 3D semiconductor device according to claim 15 ,
wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.
18 . The 3D semiconductor device according to claim 15 ,
wherein said memory control circuit comprises at least one error correcting circuit.
19 . The 3D semiconductor device according to claim 15 ,
wherein said memory control circuit comprises at least one cache memory circuit.
20 . The 3D semiconductor device according to claim 15 ,
wherein said memory control circuit comprises a memory refresh circuit.