IP Library › Granted Patent US 12666620
Granted Patent B2
US 12666620 · App. 18/457,338 · Granted Jun 23, 2026

Semiconductor device and manufacturing method of a semiconductor device

Inventors: Seok Min Choi (Gyeonggi-do, KR); Jung Shik Jang (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H10B43/35H10B41/27H10B41/35H10B43/27
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12666620
App. No.
18/457,338
Granted
Jun 23, 2026
Kind
B2
Abstract

A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.

Claims (42)

1 . A semiconductor device comprising:

a plurality of word lines;

a select line;

a channel layer extending into the select line through the word lines;

a floating gate surrounding a sidewall of the channel layer between the channel layer and the select line; and

a charge trap layer including a first and a second portion,

wherein the first portion surrounds the sidewall of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.

2 . The semiconductor device of claim 1 , wherein a select transistor is located in a region where the channel layer and the select line intersect each other, and includes the charge trap layer and the floating gate.

3 . The semiconductor device of claim 1 , wherein memory cells are located in regions where the channel layer and the word lines intersect each other, and each of the memory cells includes the charge trap layer.

4 . The semiconductor device of claim 1 , further comprising:

a first tunneling layer located between the second portion of the charge trap layer and the floating gate; and

a second tunneling layer located between the first portion of the charge trap layer and the channel layer, and extending between the channel layer and the floating gate.

5 . The semiconductor device of claim 1 , further comprising:

a blocking layer surrounding the charge trap layer.

6 . The semiconductor device of claim 1 , wherein the select line has a greater height than the word lines.

7 . The semiconductor device of claim 1 , wherein the word lines each include metal and the select line includes polysilicon.

8 . The semiconductor device of claim 1 , wherein the word lines and the select line each include metal.

9 . The semiconductor device of claim 1 , wherein the floating gate is disposed over the plurality of word lines.

10 . A semiconductor device comprising:

a gate structure including first conductive layers and insulating layers that are alternately stacked;

a second conductive layer;

an isolation structure disposed over a plurality of word lines and extending into the gate structure through the second conductive layer and a floating gate;

a channel layer extending into the gate structure through the second conductive layer, and including a cutting surface facing the isolation structure; and

the floating gate partially surrounding the channel layer and located between the channel layer and the second conductive layer.

11 . The semiconductor device of claim 10 , further comprising:

a charge trap layer surrounding the channel layer and located between the channel layer and the gate structure.

12 . The semiconductor device of claim 11 , wherein the charge trap layer extends between the floating gate and the second conductive layer.

13 . The semiconductor device of claim 11 , further comprising:

a first tunneling layer located between the floating gate and the charge trap layer.

14 . The semiconductor device of claim 11 , further comprising:

a second tunneling layer surrounding the channel layer and located between the channel layer and the charge trap layer and between the channel layer and the floating gate.

15 . The semiconductor device of claim 10 , wherein the second conductive layer and at least lowermost one of the first conductive layers are select lines, and the other first conductive layers are word lines.

16 . The semiconductor device of claim 10 , wherein the second conductive layer and at least uppermost one of the first conductive layers are select lines, and the other first conductive layers are word lines.

17 . A semiconductor device comprising:

a source line;

a bit line; and

a memory string connected between the source line and the bit line, the memory string including a first select transistor and memory cells,

wherein the first select transistor includes a charge trap layer and a floating gate, and

each of the memory cells includes the charge trap layer and does not include the floating gate.

18 . The semiconductor device of claim 17 , wherein the memory string includes a second select transistor connected between the first select transistor and the memory cells and including the charge trap layer.

19 . The semiconductor device of claim 17 , wherein the first select transistor is a source select transistor that controls a connection between the source line and the memory string.

20 . The semiconductor device of claim 17 , wherein the first select transistor is a drain select transistor that controls a connection between the bit line and the memory string.