Semiconductor device structure and methods of forming the same

1 . A method for forming a memory device, comprising:

forming a layer stack over a substrate, the layer stack comprising alternating layers of a dielectric material and an electrical conductive material;

forming first trenches in the layer stack to expose a top surface of the substrate;

forming a ferroelectric layer on exposed surfaces of the layer stack;

forming a channel layer on the ferroelectric layer, the channel layer having a first conductivity type;

filling the first trenches with a first oxide material;

forming second trenches in the first oxide material, the second trenches extending through the first oxide material to expose the top surface of the substrate;

filling the second trenches with a spacer material, the spacer material having a second conductivity type that is opposite to the first conductivity type;

removing portions of the spacer material to form spacers on opposite sides of the first oxide material and third trenches between adjacent spacers, such that the spacers are physically separated from subsequently formed source/drain features by the third trenches;

filling the third trenches with a sacrificial layer;

removing portions of the sacrificial layer to form openings in the sacrificial layer;

filling the openings with a second oxide material; and

replacing the sacrificial layers with an electrically conductive material.

2 . The method of claim 1 , wherein the channel layer and the spacer material are formed of a metal oxide semiconductor material.

3 . The method of claim 2 , wherein the removing portions of the sacrificial layer further comprises:

removing exposed portions of the channel layer to expose portions of the ferroelectric layer.

4 . The method of claim 1 , wherein the electrically conductive material forms source/drain features and are disposed immediately adjacent to the spacers.

5 . The method of claim 2 , wherein the channel layer is N-type or P-type metal oxide semiconductor material and the spacer material is P-type or N-type metal oxide semiconductor material.

6 . The method of claim 1 , further comprising:

prior to replacing the remaining sacrificial layers with an electrically conductive material, forming a barrier layer on exposed surfaces of the channel layer, the spacers, the second oxide material, and the top surface of the substrate.

7 . The method of claim 1 , wherein the first oxide material has a first length along a direction between the second trenches, and each spacer has a second length along the direction, the first length and the second length having a ratio of about 1:2 to about 5:1.

8 . The method of claim 1 , wherein the first oxide material, the spacers, and the channel layer each comprise a metal oxide semiconductor material, and the second oxide material comprises silicon oxide.

9 . The method of claim 1 , wherein after filling the openings with the second oxide material, the second oxide material is in direct contact with sidewalls of the channel layer and the ferroelectric layer.

10 . The method of claim 1 , wherein the electrically conductive material forms source lines and bit lines that are each in direct contact with the channel layer and separated from the first oxide material by the spacers.

11 . The method of claim 2 , wherein the removing portions of the sacrificial layer further comprises:

removing exposed portions of the channel layer to expose portions of the ferroelectric layer such that the second oxide material contacts the exposed portions of the ferroelectric layer.

12 . A method for forming a memory device, comprising:

forming a layer stack over a substrate, the layer stack comprising alternating layers of a dielectric material and an electrically conductive material;

forming first trenches through the layer stack to expose the substrate;

conformally forming a ferroelectric layer and a channel layer over sidewalls and a bottom of the first trenches, the channel layer having a first conductivity type;

filling the first trenches with a first oxide material to form a channel region;

forming second trenches through the first oxide material to expose the substrate;

depositing a spacer material into the second trenches, the spacer material having a second conductivity type opposite the first conductivity type;

etching the spacer material to form discrete spacers on opposing sidewalls of the first oxide material and to define third trenches between adjacent spacers, such that the spacers are physically separated from subsequently formed source/drain features by the third trenches;

filling the third trenches with a sacrificial material;

partially etching the sacrificial material and exposed portions of the channel layer to form openings exposing portions of the ferroelectric layer;

filling the openings with a second oxide material; and

prior to replacing the remaining sacrificial material with source/drain conductive features, forming a barrier layer lining the channel layer, the spacers, the second oxide material, and the exposed substrate.

13 . The method of claim 12 , wherein the partially etching the sacrificial material exposes sidewalls of the spacers such that the source/drain conductive features are immediately adjacent to but physically separated from the second oxide material by the spacers.

14 . The method of claim 12 , wherein the first oxide material has a first length and each spacer has a second length, the first length and the second length having a ratio of about 1:2 to about 5:1.

15 . The method of claim 12 , wherein the channel layer and the spacer material each comprise a metal oxide semiconductor material, and the channel layer comprises an n-type metal oxide semiconductor material while the spacer material comprises a p-type metal oxide semiconductor material.

16 . A method for forming a memory device, comprising:

forming a layer stack over a substrate, the layer stack comprising alternating layers of a dielectric material and a word line material;

forming first trenches through the layer stack to expose the substrate;

forming a ferroelectric layer and an oxide semiconductor channel layer conformally along the first trenches, the channel layer having a first conductivity type;

filling the first trenches with a first insulating material to define a channel region between the first trenches;

after filling the first trenches, forming second trenches through the first insulating material and the channel region to expose the substrate;

filling the second trenches with a second oxide semiconductor material having a second conductivity type opposite the first conductivity type to form spacers laterally adjacent to the channel region;

forming third trenches between the spacers by etching the second oxide semiconductor material, such that the spacers are physically separated from subsequently formed source/drain features by the third trenches;

filling the third trenches with a sacrificial material;

selectively etching the sacrificial material to form source/drain openings while leaving the spacers intact between the channel region and the source/drain openings;

filling the source/drain openings with a third insulating material in direct contact with sidewalls of the channel layer and the ferroelectric layer; and

replacing remaining portions of the sacrificial material with electrically conductive source/drain features such that the spacers enhance fringing electric fields in the ferroelectric layer adjacent to the channel region.

17 . The method of claim 16 , wherein the first insulating material has a first length and each spacer has a second length, the first length and the second length having a ratio of about 1:2 to about 5:1.

18 . The method of claim 16 , wherein the channel layer comprises an n-type metal oxide semiconductor material, and the second oxide semiconductor material comprises a p-type metal oxide semiconductor material.

19 . The method of claim 16 , wherein the third insulating material and the first insulating material comprise the same silicon oxide material.

20 . The method of claim 18 , further comprising:

prior to replacing the remaining portions of the sacrificial material, forming a barrier layer along exposed surfaces of the channel region, the spacers, and the third insulating material, wherein the barrier layer comprises titanium nitride or tantalum nitride.