Semiconductor device and method of manufacturing semiconductor device
A semiconductor device may include a gate structure including conductive layers and insulating layers alternately stacked, a metal channel layer extending through the gate structure, a first semiconductor channel layer extending through the gate structure and connecting to the metal channel layer, and a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.
1 . A semiconductor device comprising:
a gate structure including conductive layers and insulating layers alternately stacked;
a metal channel layer extending through the gate structure;
a first semiconductor channel layer positioned in the gate structure and connecting to the metal channel layer; and
a ferroelectric layer surrounding the metal channel layer and the first semiconductor channel layer.
2 . The semiconductor device of claim 1 , wherein a drain select transistor is positioned in a region where the first semiconductor channel layer and the conductive layers cross, and
ferroelectric memory cells are positioned in a region where the metal channel layer and the conductive layers cross.
3 . The semiconductor device of claim 1 , wherein the first semiconductor channel layer comprises:
a polysilicon layer; and
a metal silicide layer positioned between the polysilicon layer and the metal channel layer.
4 . The semiconductor device of claim 1 , further comprising:
a source line;
a source select line positioned between the source line and the gate structure; and
a second semiconductor channel layer extending through the source select line and connecting to the metal channel layer and the source line.
5 . The semiconductor device of claim 4 , wherein a drain select transistor is positioned in a region where the first semiconductor channel layer and the conductive layers cross,
a source select transistor is positioned in a region where the second semiconductor channel layer and the source select line cross, and
ferroelectric memory cells are positioned in a region where the metal channel layer and the conductive layers cross.
6 . The semiconductor device of claim 4 , wherein the conductive layers include metal, and the source select line includes polysilicon.
7 . The semiconductor device of claim 1 , further comprising:
an interface layer surrounding the ferroelectric layer.
8 . The semiconductor device of claim 7 , wherein the interface layer includes tantalum oxide (Ta 2 O 5 ).
9 . The semiconductor device of claim 1 , further comprising:
an insulating core positioned in the first semiconductor channel layer.
10 . The semiconductor device of claim 9 , wherein the first semiconductor channel layer surrounds a sidewall of the insulating core and extends between the metal channel layer and the insulating core.
11 . A semiconductor device comprising:
bit lines;
memory strings including ferroelectric memory cells including a metal channel layer and a drain select transistor including a first semiconductor channel layer;
word lines connected to the ferroelectric memory cells; and
drain select lines connected to the drain select transistor and controlling a connection of the memory strings and the bit lines.
12 . The semiconductor device of claim 11 , wherein a negative erase voltage is applied to the word lines during an erase operation.
13 . The semiconductor device of claim 12 , wherein a turn-on voltage is applied to the drain select lines and a ground voltage is applied to the bit line during the erase operation.
14 . The semiconductor device of claim 11 , wherein a program voltage is applied to a selected word line among the word lines and a pass voltage is applied to unselected word lines during a program operation.
15 . The semiconductor device of claim 14 , wherein a first bit line voltage is applied to a selected bit line among the bit lines and a second bit line voltage of a level higher than that of the first bit line voltage is applied to unselected bit lines during the program operation.
16 . The semiconductor device of claim 15 , wherein the first bit line voltage is a ground voltage.
17 . The semiconductor device of claim 15 , wherein a turn-on voltage is applied to a selected drain select line among the drain select lines and a ground voltage is applied to unselected drain select lines during the program operation.
18 . The semiconductor device of claim 11 , further comprising:
a source line; and
a source select line controlling a connection of the source line and the memory strings,
wherein each of the memory strings includes a source select transistor including a second semiconductor channel layer.
19 . The semiconductor device of claim 18 , wherein a turn-on voltage is applied to the source select line and a ground voltage is applied to the source line during an erase operation.
20 . The semiconductor device of claim 18 , wherein a ground voltage is applied to the source select line during a program operation.
21 . A semiconductor device comprising:
a gate structure including conductive layers and insulating layers alternately stacked;
a ferroelectric layer passing through the gate structure;
a metal channel layer extending through a lower portion of the gate structure; and
a first semiconductor channel layer extending through an upper portion of the gate structure, the first semiconductor channel layer being positioned over the metal channel layer with a lower surface of the first semiconductor channel layer contacting an upper surface of the metal channel layer,
wherein the ferroelectric layer laterally surrounds a side of the metal channel layer and a side of the first semiconductor channel layer.