Method of forming a memory cell having an offset interconnect via extending through a hard mask with variable thickness

1 . A method of forming an integrated chip, comprising:

forming a lower insulating structure over an interconnect within a lower dielectric structure over a substrate;

removing a part of the lower insulating structure to form an opening extending through the lower insulating structure to the interconnect;

sequentially and conformally depositing a bottom electrode layer, a data storage layer, and a top electrode layer over the lower insulating structure;

forming a hard mask over the top electrode layer, wherein the hard mask has a thickness that varies over a width of the hard mask;

patterning the bottom electrode layer, the data storage layer, and the top electrode layer to form a memory device having a data storage structure disposed between a bottom electrode and a top electrode; and

forming an interconnect via onto a substantially flat upper surface of the top electrode, wherein a center of a bottom surface of the bottom electrode is laterally separated from a center of a bottom surface of the interconnect via, wherein the interconnect via extends through the hard mask and contacts the top electrode laterally outside of a bottommost surface of the top electrode.

2 . The method of claim 1 ,

wherein the hard mask comprises curved surfaces that form a curved V-shaped region that protrudes to within the top electrode layer; and

wherein the interconnect via is laterally outside of the curved V-shaped region.

3 . The method of claim 1 , wherein the thickness varies by a greater amount above a bottommost surface of the bottom electrode layer than laterally outside of the bottommost surface of the bottom electrode layer.

4 . The method of claim 1 , wherein the top electrode layer has interior surfaces that are vertically below an upper surface of the top electrode layer and that form a recess within the upper surface of the top electrode layer.

5 . The method of claim 1 , wherein the top electrode is asymmetric about a vertically extending line bisecting the bottom surface of the bottom electrode.

6 . A method of forming an integrated chip, comprising:

depositing a lower insulating structure over an interconnect within a lower interlevel dielectric layer over a substrate;

etching the lower insulating structure to form an opening exposing the interconnect;

forming a memory device on the lower insulating structure, wherein the memory device comprises a switching structure disposed between a bottom electrode and a top electrode, a part of the memory device being arranged within the opening;

forming an interconnect via onto the top electrode, wherein a bottommost surface of the interconnect via is laterally outside of the opening;

forming a hard mask over the top electrode, wherein the hard mask comprises a first region over the opening and a second region laterally outside of the opening, the first region having a thickness that varies over a first range of vertical thicknesses and the second region having a thickness that varies over a second range of vertical thicknesses that is smaller than the first range of vertical thicknesses;

forming a protective layer continuously extending from over the hard mask to along opposing sides of the memory device; and

covering the protective layer with an inter-level dielectric layer, wherein the interconnect via extends through the second region of the hard mask, the inter-level dielectric layer, and the protective layer.

7 . The method of claim 6 , wherein the hard mask comprises curved surfaces that meet at a point over a bottommost surface of the bottom electrode.

8 . The method of claim 7 , wherein the top electrode has a bottommost surface that continuously extends in opposing directions to non-zero distances past the point.

9 . The method of claim 6 , wherein a bottommost surface of the bottom electrode and the bottommost surface of the interconnect via are both laterally off-centered from a center of the memory device in a cross-sectional view.

10 . The method of claim 6 ,

wherein a bottommost surface of the bottom electrode is arranged laterally between a center of the memory device and a first outermost sidewall of the memory device; and

wherein the bottommost surface of the interconnect via is arranged laterally between the center of the memory device and a second outermost sidewall of the memory device that opposes the first outermost sidewall.

11 . The method of claim 6 ,

wherein a bottommost surface of the bottom electrode is laterally separated from the bottommost surface of the interconnect via along a first direction; and

wherein the bottommost surface of the bottom electrode and the bottommost surface of the interconnect via have opposing outermost edges that are substantially aligned along a second direction that is perpendicular to the first direction in a top-view.

12 . The method of claim 6 , wherein the bottom electrode comprises an upper surface that laterally extends past opposing outermost sidewalls of the switching structure.

13 . The method of claim 6 , wherein the protective layer extends to within a divot in an upper surface of the hard mask and the inter-level dielectric layer extends to within a divot in an upper surface of the protective layer.

14 . The method of claim 13 , further comprising:

depositing a capacitive switching layer on sidewalls and an upper surface of the bottom electrode; and

depositing the top electrode on sidewalls and an upper surface of the switching structure.

15 . A method of forming an integrated chip, comprising:

depositing a dielectric structure over an interconnect;

etching the dielectric structure to form an opening exposing the interconnect;

depositing a bottom electrode layer on the dielectric structure and within the opening;

depositing a capacitive switching layer on the bottom electrode layer;

depositing a top electrode layer on the capacitive switching layer;

depositing a hard mask over the top electrode layer, the hard mask comprising a first region that is over the opening and that has a variable thickness and a second region that is laterally outside of the opening and that has a substantially constant thickness;

performing a first patterning process on the top electrode layer to form a top electrode;

forming dielectric spacers along opposing sides of the top electrode after performing the first patterning process;

performing a second patterning process on the bottom electrode layer to form a bottom electrode; and

forming an interconnect via onto the top electrode, wherein the interconnect via extends through the second region of the hard mask.

16 . The method of claim 15 , further comprising:

forming a dielectric extending from within a recess that is within an upper surface of the hard mask to along opposing sides of the interconnect via.

17 . The method of claim 15 , wherein the hard mask comprises a protrusion extending outward from a lower surface of the hard mask to within a recess in the top electrode, the interconnect via being laterally outside of the protrusion.

18 . The method of claim 17 , wherein the protrusion completely fills the recess in the top electrode.

19 . The method of claim 15 , wherein the interconnect via contacts the top electrode along a surface of the top electrode that is below a topmost surface of the top electrode.

20 . The method of claim 15 , wherein a bottom surface of the top electrode is below a top surface of the dielectric structure.