Memory device and method of forming the same and integrated circuit

1 . A memory device, comprising:

a selector, comprising a first electrode layer, a second electrode layer and a selector layer between the first electrode and the second electrode, wherein the selector layer comprises a first element selected from a group consisting of silicon (Si), germanium (Ge), tin (Sn) and aluminum (Al), a second element selected from a group consisting of oxygen (O) and nitrogen (N), and a third element selected from a group consisting of tellurium (Te), selenium (Se) and antimony (Sb), wherein a thickness of the selector layer is in a range of 2 nm to 25 nm; and

a memory cell, comprising a data storage layer over the selector layer.

2 . The memory device of claim 1 , wherein an atomic percentage of the first element in the selector layer is in a range of 15% to 40%, an atomic percentage of the second element in the selector layer is in a range of 40% to 70%, and an atomic percentage of the third element in the selector layer is in a range of 10% to 40%.

3 . The memory device of claim 1 , wherein a threshold voltage of the selector layer is in a range of 0.8 V to 1.5 V.

4 . The memory device of claim 1 , wherein the selector layer is in direct contact with the data storage layer.

5 . The memory device of claim 1 further comprising a first interfacial layer between the selector layer and the first electrode layer.

6 . The memory device of claim 5 further comprising a second interfacial layer between the selector layer and the second electrode layer.

7 . The memory device of claim 1 , wherein the memory cell comprises a RRAM cell or a PCRAM cell.

8 . An integrated circuit, comprising:

a substrate;

an array overlying the substrate and comprising multiple stacks in a plurality of rows and a plurality of columns, each of the stacks comprising a memory cell and a selector, wherein a selector layer of the selector comprises a first element selected from a group consisting of silicon (Si), germanium (Ge), tin (Sn) and aluminum (Al), a second element selected from a group consisting of oxygen (O) and nitrogen (N), and a third element being selenium (Se);

a plurality of bit lines, extending along corresponding columns of the array in a first direction, wherein the bit lines overlie the stacks and are electrically coupled with memory cells of the array in the corresponding columns; and

a plurality of word lines, extending along corresponding rows of the array in a second direction transverse the first direction, wherein the word lines underlie the stacks and are electrically coupled with memory cells of the array in the corresponding rows.

9 . The integrated circuit of claim 8 , further comprising an interconnect structure overlying the substrate, wherein the interconnect structure includes a plurality of conductive wires and a plurality of conductive vias disposed within a dielectric layer.

10 . The integrated circuit of claim 8 , wherein the memory cell is a resistive switching memory cell.

11 . The integrated circuit of claim 8 , wherein the memory cell is disposed over the selector.

12 . The integrated circuit of claim 8 , wherein a first electrode layer of the memory cell is in direct contact with the corresponding bit line, and a second electrode layer of the selector is direct contact with the corresponding word line.

13 . A method of forming a memory device, comprising:

forming a first electrode layer;

forming a selector layer over the first electrode layer, wherein the selector layer comprises a first element selected from a group consisting of silicon (Si), germanium (Ge), tin (Sn) and aluminum (Al), a second element selected from a group consisting of oxygen (O) and nitrogen (N), and a third element being selenium (Se) ; and

forming a second electrode layer over the selector layer.

14 . The method of claim 13 , wherein forming the selector layer comprises co-sputtering the first element, the second element and the third element.

15 . The method of claim 13 , wherein forming the selector layer comprises:

co-sputtering the first element and the third element; and

introducing a gas containing the second element.

16 . The method of claim 15 , wherein introducing the gas containing the second element is performed simultaneously with or after co-sputtering the first element and the third element.

17 . The method of claim 13 , wherein forming the selector layer comprises co-sputtering the third element and a compound comprising the first element and the second element.

18 . The method of claim 17 , wherein the compound is silicon oxide.

19 . The memory device of claim 1 , wherein the third element is selenium (Se).

20 . The method of claim 13 , wherein the selector layer is formed by a pulsed laser deposition (PLD) process.