Semiconductor contact structures and methods

1 . A method comprising:

forming a fin protruding from a substrate;

forming a gate structure extending over the fin;

forming a source/drain region in the fin adjacent the gate structure;

forming a first isolation region over the source/drain region;

forming a first mask layer over the gate structure;

etching the first isolation region using the first mask layer as an etch mask to form a first recess;

conformally depositing a second mask layer over the first mask layer and within the first recess;

depositing a third mask layer over the second mask layer;

etching the third mask layer, the second mask layer, and the first isolation region to form a second recess that exposes the source/drain region; and

depositing a conductive material in the second recess.

2 . The method of claim 1 further comprising performing a planarization process on the gate structure and the conductive material, wherein after performing the planarization process, top surfaces of the gate structure and the conductive material are level.

3 . The method of claim 1 , wherein etching the first isolation region to form the first recess exposes a sidewall of the gate structure.

4 . The method of claim 1 further comprising:

forming a second isolation region over the conductive material and the gate structure; and

forming a conductive feature that penetrates the second isolation region to physically and electrically contact the conductive material.

5 . The method of claim 4 , wherein the conductive feature also physically and electrically contacts the gate structure.

6 . The method of claim 4 further comprising forming a gate contact that penetrates the second isolation region to physically and electrically contact the gate structure, wherein top surfaces of the gate contact and the conductive feature are level.

7 . The method of claim 1 , wherein the first recess has a depth in the range of 9 nm to 54 nm from a top surface of the first mask layer.

8 . The method of claim 1 , wherein the first mask layer comprises a metal oxide.

9 . A method comprising:

forming a plurality of gate stacks on a semiconductor fin;

forming a plurality of epitaxial source/drain regions in the semiconductor fin, wherein each epitaxial source/drain region is adjacent a respective gate stack;

depositing a first dielectric layer over the plurality of epitaxial source/drain regions;

forming a plurality of capping layers on the plurality of gate stacks, wherein each capping layer is on a respective gate stack;

recessing the first dielectric layer using a first etching process, wherein the first etching process exposes sidewalls of the plurality of gate stacks;

depositing a conformal dielectric layer on the plurality of capping layers and on sidewalls of the plurality of gate stacks;

recessing the conformal dielectric layer and the first dielectric layer to expose top surfaces of the plurality of epitaxial source/drain regions;

forming a plurality of source/drain contacts on the top surfaces of the plurality of epitaxial source/drain regions; and

removing upper portions of the plurality of gate stacks and the plurality of source/drain contacts using a planarization process.

10 . The method of claim 9 , wherein the first etching process selectively etches the first dielectric layer at a greater rate than the plurality of capping layers.

11 . The method of claim 9 , wherein the conformal dielectric layer physically contacts a top surface of the first dielectric layer.

12 . The method of claim 9 further comprising depositing a second dielectric layer on the conformal dielectric layer.

13 . The method of claim 12 , wherein the second dielectric layer comprises amorphous silicon.

14 . The method of claim 13 further comprising implanting upper portions of the second dielectric layer with a dopant.

15 . The method of claim 9 , wherein the first etching process forms a polymer over the plurality of capping layers.

16 . The method of claim 9 , wherein the planarization process leaves top surfaces of the plurality of gate stacks level with top surfaces of the plurality of source/drain contacts.

17 . A device comprising:

a semiconductor fin comprising a channel region between a first source/drain region and a second source/drain region;

a gate stack over the channel region of the semiconductor fin;

a first contact on the first source/drain region and a second contact on the second source/drain region, wherein top surfaces of the first contact, the second contact, and the gate stack are level;

an etch stop layer over the first contact, the second contact, and the gate stack;

a first interlayer dielectric (ILD) layer over the etch stop layer; and

a first conductive via extending through the first ILD layer and the etch stop layer to interface and electrically contact the first contact.

18 . The device of claim 17 further comprising a second conductive via in the first ILD layer that physically and electrically contacts the gate stack, wherein the second conductive via is taller than the first conductive via.

19 . The device of claim 17 , wherein the first conductive via physically and electrically contacts the second contact, wherein a portion of the first conductive via is between a sidewall of the first source/drain region and a sidewall of the second source/drain region.

20 . The device of claim 17 , wherein the first conductive via also physically and electrically contacts the gate stack.