Gate all-around (GAA) field effect transistors (FETS) having vertical source and drain
A semiconductor device, includes: (a) a substrate, (b) a gate electrode, disposed on a surface of the substrate, and including a plate, orthogonal to the surface, and having openings, a longest axis of the openings is orthogonal to the surface, and (c) elements having a shape that fits in the openings, the elements (i) are orthogonal both to the surface and to the gate electrode, (ii) extend through the openings, and (iii) are surrounded by the gate electrode and spaced away from the surface, the elements including: a first section that is located on a first side of the gate electrode and serves as a source; and a second section that is located on a second side of the gate electrode and serves as a drain, the gate electrode configured to control movement of charge carriers between the source and the drain in response to an applied electrical signal.
1 . A semiconductor device, comprising:
a semiconductor substrate;
a gate electrode disposed on a surface of the semiconductor substrate, the gate electrode comprising a plate, which is orthogonal to the surface, and having one or more openings, wherein a longest axis of at least one of the openings is orthogonal to the surface, wherein the one or more openings of the gate electrode have a rectangular shape;
one or more nanosheets having a rectangular cross section and a shape that fits in the one or more openings, respectively, the one or more nanosheets (i) are orthogonal both to the surface and to the gate electrode, (ii) extend through the one or more openings, respectively, and (iii) are surrounded by the gate electrode and spaced away from the surface, the one or more nanosheets comprising: (i) a first section that is located on a first side of the gate electrode and serves as a source, and (ii) a second section that is located on a second side of the gate electrode and serves as a drain, the gate electrode being configured to control movement of charge carriers between the source and the drain in response to an applied electrical signal;
first contacts comprising first and second plates, the first and second plates being disposed along first and second sides of the gate electrode, respectively, wherein the first plate is configured to electrically connect between the source and a first power source, and the second plate is configured to electrically connect between the drain and a second power source, wherein at least one of the first and second plates is: (i) disposed around the one or more nanosheets, and (ii) coplanar with the gate electrode; and
one or more second contacts, the one or more second contacts being configured to electrically connect between the gate electrode and a third power source.
2 . The semiconductor device according to claim 1 , comprising a gate dielectric layer, which is disposed at the opening between the gate electrode and the nanosheets to form a gate all-around (GAA) field effect transistor (FET) having a vertical channel on one or more surfaces of the nanosheets between the source and the drain.
3 . The semiconductor device according to claim 1 , wherein the gate electrode and at least one of the nanosheets form a first gate all-around (GAA) field effect transistor (FET) having a first polarity, the semiconductor device further comprising a second GAA FET that is stacked over the first GAA FET, the second GAA FET having a second polarity that is different from the first polarity.
4 . A semiconductor device, comprising:
a semiconductor substrate;
a gate electrode disposed on a surface of the semiconductor substrate, the gate electrode comprising a plate, which is orthogonal to the surface, and having one or more openings, wherein a longest axis of at least one of the openings is orthogonal to the surface, wherein the one or more openings of the gate electrode have a rectangular shape; and
one or more nanosheets having a rectangular cross section and a shape that fits in the one or more openings, respectively, the one or more nanosheets (i) are orthogonal both to the surface and to the gate electrode, (ii) extend through the one or more openings, respectively, and (iii) are surrounded by the gate electrode and spaced away from the surface, the one or more nanosheets comprising: (i) a first section that is located on a first side of the gate electrode and serves as a source, and (ii) a second section that is located on a second side of the gate electrode and serves as a drain, the gate electrode being configured to control movement of charge carriers between the source and the drain in response to an applied electrical signal;
wherein the gate electrode and at least one of the nanosheets form a first gate all-around (GAA) field effect transistor (FET) having a first polarity, the semiconductor device further comprising a second GAA FET that is stacked over the first GAA FET, the second GAA FET having a second polarity that is different from the first polarity; and
wherein the second GAA FET comprises:
an additional gate electrode, the additional gate electrode comprising an additional plate that orthogonal to the surface and that is coplanar with the gate electrode of the first GAA FET; and
one or more additional nanosheets, the additional nanosheets (i) being orthogonal both to the surface and to the additional gate electrode, (ii) extending through at least one opening in the additional gate electrode, and (iii) being surrounded by the additional gate electrode and spaced away from the nanosheets of the first GAA FET.
5 . The semiconductor device according to claim 4 and comprising electrical contacts which extend from at least the gate electrode of the first GAA FET and which pass alongside the second GAA FET, the electrical contacts being configured to connect between the first GAA FET and a power source.
6 . The semiconductor device according to claim 5 , wherein the first GAA FET has a first footprint on the surface, wherein the second GAA FET has a second footprint on the surface that is smaller than and contained within the first footprint, wherein the electrical contacts have a third footprint on the surface, falling within the first footprint but outside the second footprint.
7 . The semiconductor device according to claim 3 and comprising a dielectric layer, the dielectric layer being: (i) disposed between the first GAA FET and the second GAA FET, and (ii) configured to electrically isolate between the first GAA FET and the second GAA FET.
8 . A method for fabricating a semiconductor device, the method comprising:
disposing, on a surface of a semiconductor substrate, a gate electrode comprising a plate, which is orthogonal to the surface, the plate having one or more openings, wherein a longest axis of at least one of the openings is orthogonal to the surface, wherein the one or more openings of the gate electrode have a rectangular shape;
forming one or more nanosheets having a rectangular cross section corresponding to the rectangular shape of the one or more openings, the one or more nanosheets (i) being orthogonal both to the surface and to the gate electrode, (ii) extending through the one or more openings, respectively, and (iii) being surrounded by the gate electrode and spaced away from the surface, forming the one or more nanosheets comprises (i) positioning a first section of the one or more nanosheets on a first side of the gate electrode to serve as a source, and (ii) positioning a second section of the one or more nanosheets on a second side of the gate electrode to serve as a drain;
forming, along first and second sides of the gate electrode, first contacts comprising first and second plates, respectively, the first plate for electrically connecting between the source and a first power source, and the second plate for electrically connecting between the drain and a second power source, wherein forming at least one of the first and second plates comprises forming the at least one of the first and second plates (i) around the one or more nanosheets, and (ii) coplanar with the gate electrode; and
forming one or more second contacts for electrically connecting between the gate electrode and a third power source.
9 . The method according to claim 8 , wherein forming the one or more nanosheets comprises: (i) disposing on the semiconductor substrate at least a semiconductor layer and a stack of dielectric layers, (ii) patterning a mandrel mask in at least one of the dielectric layers of the stack, (iii) patterning a spacer at sidewalls of the mandrel mask and removing the mandrel mask, and (iv) patterning the nanosheets in the semiconductor layer by transferring a pattern of the spacer to the semiconductor layer.
10 . The method according to claim 8 and comprising disposing at the opening, between the gate electrode and the nanosheets, a gate dielectric layer for producing a gate all-around (GAA) field effect transistor (FET) having a vertical channel on one or more surfaces of the nanosheets.
11 . The method according to claim 8 , wherein the gate electrode and at least one of the nanosheets form a first gate all-around (GAA) field effect transistor (FET) having a first polarity, comprising forming a second GAA FET, which is stacked over the first GAA FET and has a second polarity, different from the first polarity.
12 . The method according to claim 11 and comprising forming electrical contacts extending from at least the gate electrode of the first GAA FET and pass alongside the second GAA FET, the electrical contacts being configured to connect between the first GAA FET and a power source.
13 . The method according to claim 12 , wherein forming the first GAA FET comprises disposing the first GAA FET having a first footprint on the surface, wherein forming the second GAA FET comprises disposing the second GAA FET having a second footprint on the surface, smaller than and contained within the first footprint, and wherein forming the electrical contacts comprises positioning the electrical contacts having a third footprint on the surface, falling within the first footprint but outside the second footprint.
14 . The method according to claim 11 and comprising forming a dielectric layer between the first GAA FET and the second GAA FET to electrically isolate between the first GAA FET and the second GAA FET.