IP Library Granted Patent US 12666640
Granted Patent B2
US 12666640 · App. 18/171,362 · Granted Jun 23, 2026

Low-frequency nosie transistors with curved channels

Inventors: Wen-Chao Shen (Hsinchu, TW); Shih-Chang Chen (Chiayi County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D30/611H10D30/023H10D30/024H10D30/62H10D64/518
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Quick Facts
Patent No.
US 12666640
App. No.
18/171,362
Granted
Jun 23, 2026
Kind
B2
Abstract

A transistor includes: a substrate; a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section; a first drain and a second drain; a first source and a second source; a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.

Claims (36)

1 . A transistor comprising:

a substrate;

a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section;

a first drain and a second drain located at the first straight section of the first fin and the first straight section of the second fin, respectively;

a first source and a second source located at the second straight section of the first fin and the second straight section of the second fin, respectively;

a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and

a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.

2 . The transistor of claim 1 , wherein the first curved section and the second curved section of the first fin are round corner sections.

3 . The transistor of claim 2 , wherein the first curved section and the second curved section of the second fin are round corner sections.

4 . The transistor of claim 1 , wherein the first curved channel and the second curved channel are located in a first gate region and controlled by a first gate structure.

5 . The transistor of claim 4 , wherein the third curved channel and the fourth curved channel are located in a second gate region and controlled by a second gate structure.

6 . The transistor of claim 1 , wherein the first curved section of the first fin is characterized by that a maximum fin height of the first curved section of the first fin deviates a minimum fin height of the first curved section of the first fin by above 5%.

7 . The transistor of claim 1 , wherein the first curved section of the first fin is characterized by that a maximum fin width of the first curved section of the first fin deviates a minimum fin width of the first curved section of the first fin by above 5%.

8 . The transistor of claim 1 , wherein the first curved section of the first fin is characterized by that a maximum fin height of the first curved section of the first fin deviates a minimum fin height of the first curved section of the first fin by above 5%, a maximum fin width of the first curved section of the first fin deviates a minimum fin width of the first curved section of the first fin by above 5%.

9 . The transistor of claim 1 , wherein the first drain and the second drain are connected to a source contact, and wherein the first source and the second source are connected to a source contact.

10 . A transistor comprising:

a substrate;

at least one fin protruding upwardly from a top surface of the substrate, wherein the at least one fin comprises a first fin and a second fin, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section;

at least one drain located at the first fin or the second fin;

at least one source located at the first fin or the second fin; and

at least one curved channel located at the first curved section or the second curved section of the first fin or the second fin.

11 . The transistor of claim 10 , wherein the first curved section of the first fin is characterized by that a maximum fin height of the first curved section deviates a minimum fin height of the first curved section by above 5%.

12 . The transistor of claim 10 , wherein the first curved section of the first fin is characterized by that a maximum fin width of the first curved section deviates a minimum fin width of the first curved section by above 5%.

13 . A method comprising:

forming a substrate;

forming a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section;

forming a first drain and a second drain located at the first straight section of the first fin and the first straight section of the second fin, respectively;

forming a first source and a second source located at the second straight section of the first fin and the second straight section of the second fin, respectively;

forming a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and

forming a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.

14 . The method of claim 13 , wherein the first curved section and the second curved section of the first fin are round corner sections.

15 . The method of claim 14 , wherein the first curved section and the second curved section of the second fin are round corner sections.

16 . The method of claim 13 , wherein the first curved channel and the second curved channel are located in a first gate region and controlled by a first gate structure.

17 . The method of claim 16 , wherein the third curved channel and the fourth curved channel are located in a second gate region and controlled by a second gate structure.

18 . The method of claim 13 , wherein the first curved section of the first fin is characterized by that a maximum fin height of the first curved section of the first fin deviates a minimum fin height of the first curved section of the first fin by above 5%.

19 . The method of claim 13 , wherein the first curved section of the first fin is characterized by that a maximum fin width of the first curved section of the first fin deviates a minimum fin width of the first curved section of the first fin by above 5%.