Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate having fins and trenches in between the fins, a plurality of insulators, a first metal layer, an insulating layer, a second metal layer and an interlayer dielectric. The insulators are disposed within the trenches of the substrate. The first metal layer is disposed on the plurality of insulators and across the fins. The insulating layer is disposed on the first metal layer over the plurality of insulators and across the fins. The second metal layer is disposed on the insulating layer over the plurality of insulators and across the fins. The interlayer dielectric is disposed on the insulators and covering the first metal layer, the insulating layer and the second metal layer.
1 . A semiconductor device, comprising:
a substrate having fins and trenches in between the fins;
a plurality of insulators disposed within the trenches of the substrate;
a first metal layer disposed on the plurality of insulators and across the fins;
an insulating layer disposed on the first metal layer over the plurality of insulators and across the fins;
a second metal layer disposed on the insulating layer over the plurality of insulators and across the fins;
an interlayer dielectric disposed on the plurality of insulators and covering the first metal layer, the insulating layer and the second metal layer; and
strained material portions disposed on two opposing sides of the first metal layer, the insulating layer and the second metal layer, wherein top surfaces of the strained material portions are located above top surfaces of the first metal layer and the insulating layer, and a top surface of the second metal layer is located above the top surfaces of the strained material portions.
2 . The semiconductor device according to claim 1 , wherein the interlayer dielectric is physically contacting sidewalls of the first metal layer, and physically contacting and covering the strained material portions.
3 . The semiconductor device according to claim 1 , wherein the first metal layer is in physical contact with the strained material portions.
4 . The semiconductor device according to claim 1 , wherein the first metal layer and the insulating layer is in physical contact with the strained material portions, and the second metal layer is physically separated from the strained material portions by spacer structures.
5 . The semiconductor device according to claim 1 , further comprising a gate dielectric layer disposed in between the insulating layer and the second metal layer, and across the fins.
6 . The semiconductor device according to claim 1 , further comprising:
a second insulating layer and a third insulating layer disposed in between the insulating layer and the second metal layer, and across the fins.
7 . The semiconductor device according to claim 1 , further comprising:
a source contact and a drain contact disposed on two opposing sides of the second metal layer, and wherein the first metal layer is in direct contact with the source contact and the drain contact.
8 . The semiconductor device according to claim 1 , further comprising:
a second insulating layer disposed on the second metal layer and over the fins;
a third metal layer disposed on the second insulating layer and over the fins;
a third insulating layer disposed on the third metal layer and over the fins; and
a fourth metal layer disposed on the third insulating layer and over the fins,
wherein the first metal layer and third metal layer are electrically connected to source region materials of the semiconductor device, and the second metal layer and the fourth metal layer are electrically connected to drain region materials of the semiconductor device.
9 . A semiconductor device, comprising:
a logic region and a capacitor region, wherein
the capacitor region comprises:
a substrate having fins;
a first metal layer and a second metal layer disposed on the fins;
at least one insulating layer disposed in between the first metal layer and the second metal layer and on the fins; and
spacer structures disposed on a top surface of the at least one insulating layer, and over a top surface of the first metal layer, and covering sidewalls of the second metal layer;
the logic region comprises:
the substrate having the fins;
a gate dielectric disposed on the fins, wherein a thickness of the gate dielectric is greater than a thickness of the at least one insulating layer; and
a gate electrode disposed on the gate dielectric.
10 . The semiconductor device according to claim 9 , wherein the at least one insulating layer comprises a first insulating layer in contact with the first metal layer, and a gate insulating layer disposed on the first insulating layer and in contact with the second metal layer.
11 . The semiconductor device according to claim 10 , further comprising a second insulating layer disposed in between the first insulating layer and the gate insulating layer.
12 . The semiconductor device according to claim 9 , further comprising a source contact and a drain contact disposed on two opposing sides of the second metal layer, wherein the second metal layer is spaced apart from the source contact and the drain contact through the spacer structures.
13 . The semiconductor device according to claim 12 , wherein the source contact and the drain contact is in physical contact with the first metal layer.
14 . The semiconductor device according to claim 12 , further comprising strained material portions disposed below the source contact and the drain contact and wherein the at least one insulating layer is physically contacting the strained material portions.
15 . The semiconductor device according to claim 9 , wherein the fins in the logic region and the fins in the capacitor region have different heights.
16 . A method of fabricating a semiconductor device,
providing a substrate;
patterning the substrate to form trenches in the substrate and fins between the trenches;
forming a plurality of insulators in the trenches of the substrate;
forming a first metal layer on the plurality of insulators and across the fins;
forming an insulating layer on the first metal layer and over the plurality of insulators and across the fins;
forming a second metal layer on the insulating layer and over the plurality of insulators and across the fins;
forming an interlayer dielectric on the plurality of insulators and covering and contacting sidewalls of the first metal layer and the insulating layer, and physically separated from the second metal layer.
17 . The method according to claim 16 , further comprising:
forming strained material portions on two opposing sides of the first metal layer, the insulating layer and the second metal layer.
18 . The method according to claim 17 , wherein the first metal layer is formed to be in physical contact with the strained material portions.
19 . The method according to claim 17 , wherein the first metal layer and the insulating layer are formed to be in physical contact with the strained material portions, and the second metal layer is formed to be physically separated from the strained material portions by spacer structures.
20 . The method according to claim 16 , further comprising:
forming a second insulating layer and a third insulator layer in between the insulating layer and the second metal layer, and across the fins.