Multiple silicide process for separately forming n-type and p-type ohmic contacts and related devices
A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region. A first ohmic contact comprising a first conductive material is formed on the source region. A second ohmic contact comprising a second conductive material, which is different than the first conductive material, is formed on the well contact region. A gate structure is formed on the drift region and includes a gate contact comprising a third conductive material, which is different than the first and second conductive material. Related devices and fabrication methods are also discussed.
1 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type;
a first ohmic contact comprising a first conductive material on the source region;
a second ohmic contact that is distinct from the first ohmic contact, the second ohmic contact comprising a second conductive material on the well contact region, wherein the second conductive material is different than the first conductive material;
at least one contact plug that is on the first and/or second ohmic contacts, wherein the at least one contact plug electrically connects the first and second ohmic contacts; and
a gate structure comprising a gate contact comprising a third conductive material, wherein the third conductive material is different than the first and second conductive materials.
2 . The power semiconductor device of claim 1 , further comprising:
a dielectric layer on a surface of the semiconductor layer structure,
wherein the dielectric layer laterally extends onto an upper surface of an edge of the first ohmic contact.
3 . The power semiconductor device of claim 1 , wherein a surface of the well contact region comprises a step difference relative to a surface of the source region.
4 . The power semiconductor device of claim 3 , wherein the step difference is greater than about 10 nanometers (nm) and less than about 100 nm.
5 . The power semiconductor device of claim 1 , wherein a first contact resistance of the first ohmic contact and a second contact resistance of the second ohmic contact are less than about 1×10 −3 ohm-cm 2 .
6 . The power semiconductor device of claim 5 , wherein the first contact resistance is about 1×10 −6 ohm-cm 2 to about 5×10 −7 ohm-cm 2 , and wherein the second contact resistance is about 1×10 −4 ohm-cm 2 to about 5×10 −7 ohm-cm 2 .
7 . The power semiconductor device of claim 1 , wherein the semiconductor layer structure comprises silicon carbide, and wherein the first, second, and third conductive materials comprise first, second, and third metal silicides, respectively.
8 . The power semiconductor device of claim 1 , wherein the first and second ohmic contacts comprise at least one dimension that is about 2 micrometers (μm) to about 1 μm.
9 . The power semiconductor device of claim 1 , further comprising:
a protective spacer that is directly on the semiconductor layer structure and extends along a sidewall of the gate structure.
10 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type, wherein the semiconductor layer structure comprises silicon carbide;
a first ohmic contact comprising a first conductive silicide on the source region;
a second ohmic contact comprising a second conductive silicide on the well contact region, wherein the second conductive silicide is different than the first conductive silicide; and
a gate structure comprising a gate contact comprising a third conductive silicide, wherein the third conductive silicide is different than the first and second conductive silicides,
wherein the first conductive silicide comprises nickel, wherein the second conductive silicide comprises at least one of nickel, aluminum, or titanium, and wherein the third conductive silicide comprises at least one of tantalum, tungsten, titanium, or cobalt.
11 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region;
a first ohmic contact comprising a first conductive material on the source region;
a second ohmic contact that is distinct from the first ohmic contact, the second ohmic contact comprising a second conductive material on the well contact region, wherein the second conductive material is different than the first conductive material; and
at least one contact plug that is on the first and/or second ohmic contacts, wherein the at least one contact plug electrically connects the first and second ohmic contacts,
wherein, in plan view, the first and second ohmic contacts comprise at least one dimension that is less than about 2 micrometers (μm).
12 . The power semiconductor device of claim 11 , wherein the semiconductor layer structure comprises silicon carbide, and wherein the first and second conductive materials comprise first and second metal silicides, respectively.
13 . The power semiconductor device of claim 12 , further comprising:
a gate structure on the drift region adjacent the source region;
a protective spacer on a sidewall of the gate structure; and
a gate contact on the gate structure, wherein the gate contact comprises a third metal silicide that is different from the first and second metal silicides.
14 . The power semiconductor device of claim 11 , wherein a first contact resistance of the first ohmic contact and a second contact resistance of the second ohmic contact are less than about 1×10 −3 ohm-cm 2 and greater than about 5×10 −7 ohm-cm 2 .
15 . The power semiconductor device of claim 11 , wherein the at least one dimension of the first and second contacts is greater than about 1 μm.
16 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region;
a first ohmic contact comprising a first conductive material on the source region;
a second ohmic contact comprising a second conductive material on the well contact region, wherein the second conductive material is different than the first conductive material; and
a dielectric layer on a surface of the semiconductor layer structure,
wherein the dielectric layer laterally extends onto an upper surface of an edge of the first ohmic contact.
17 . The power semiconductor device of claim 16 , wherein the semiconductor layer structure comprises silicon carbide, and wherein the first and second conductive materials comprise first and second metal silicides, respectively.
18 . The power semiconductor device of claim 17 , further comprising:
a gate structure on the drift region adjacent the source region;
a protective spacer on a sidewall of the gate structure; and
a gate contact on the gate structure, wherein the gate contact comprises a third metal silicide that is different from the first and second metal silicides.
19 . The power semiconductor device of claim 18 , wherein the third metal silicide has a lower silicidation temperature than the first metal silicide.
20 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region;
a first ohmic contact comprising a first conductive material on the source region; and
a second ohmic contact comprising a second conductive material on the well contact region,
wherein the first and second ohmic contacts are on first and second portions of a surface of the semiconductor layer structure, respectively, and
wherein the second portion of the surface comprises a step difference relative to the first portion of the surface.
21 . The power semiconductor device of claim 20 , wherein the semiconductor layer structure comprises silicon carbide, and wherein the first and second conductive materials are different and comprise first and second metal silicides, respectively.
22 . The power semiconductor device of claim 21 , further comprising:
a gate structure on the drift region adjacent the source region;
a protective spacer on a sidewall of the gate structure; and
a gate contact on the gate structure, wherein the gate contact comprises a third metal silicide that is different from the first and second metal silicides.
23 . The power semiconductor device of claim 22 , wherein the third metal silicide has a higher silicidation temperature than the first or second metal silicide.
24 . A power semiconductor device, comprising:
a semiconductor layer structure comprising a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region;
a first ohmic contact comprising a first conductive material on the source region; and
a second ohmic contact that is distinct from the first ohmic contact, the second ohmic contact comprising a second conductive material on the well contact region, wherein the second conductive material has a different annealing temperature than the first conductive material; and
at least one contact plug that is on the first and/or second ohmic contacts,
wherein a first contact resistance of the first ohmic contact and a second contact resistance of the second ohmic contact are less than about 1×10 −3 ohm-cm 2 .
25 . The power semiconductor device of claim 24 , wherein the first contact resistance is about 1×10 −6 ohm-cm 2 to about 5×10 −7 ohm-cm 2 , and wherein the second contact resistance is about 1×10 −4 ohm-cm 2 to about 5×10 −7 ohm-cm 2 .
26 . The power semiconductor device of claim 25 , wherein the semiconductor layer structure comprises silicon carbide, and wherein the first and second conductive materials comprise first and second metal silicides, respectively.
27 . The power semiconductor device of claim 26 , further comprising:
a gate structure on the drift region adjacent the source region; and
a gate contact on the gate structure, wherein the gate contact comprises a third metal silicide that is different from the first and second metal silicides, and wherein the gate contact has a third contact resistance of about 1×10 −3 ohm-cm 2 to about 5×10 −7 ohm-cm 2 .
28 . The power semiconductor device of claim 24 , wherein the at least one contact plug electrically connects the first and second ohmic contacts.