Semiconductor structure facilitating prevention of a parasitic device and method for forming same
A semiconductor structure and a method for forming the same are provided. One form of a method includes: forming a source/drain groove in the channel structure on two sides of a gate structure; forming a sacrificial epitaxial layer on a bottom of the source/drain groove; forming, on the sacrificial epitaxial layer, a source/drain doped layer in the source/drain groove; and removing the sacrificial epitaxial layer, to form a gap between a bottom of the source/drain doped layer and the protrusion. After the sacrificial epitaxial layer is formed, the source/drain doped layer located in the source/drain groove may be formed on the sacrificial epitaxial layer using the epitaxy process on the basis of the sacrificial epitaxial layer. Therefore, the epitaxy process for forming the source/drain doped layer is prevented from adverse effects, the epitaxial growth quality of the source/drain doped layer is ensured, and a performance of the semiconductor structure is optimized.
1 . A semiconductor structure, comprising:
a base, comprising a substrate and a plurality of protruding structures separately disposed on the substrate, wherein each protruding structure of the plurality of protruding structures comprises a protrusion and a channel structure located on the protrusion;
an isolation layer, located on the substrate and surrounding the protrusion on each protruding structure of the plurality of protruding structures, wherein a top surface of the isolation layer is lower than a top surface of the protruding structures of the plurality of protruding structures;
a device gate structure, located on the isolation layer and spanning the channel structure of the protruding structures of the plurality of protruding structures; and
source/drain doped layers, located in the channel structure of the protruding structures of the plurality of protruding structures on two sides of the device gate structure, wherein a gap is formed between a bottom of each source/drain doped layer and the protrusion, the gap is defined by at least a bottom surface of the source/drain doped layer and a top surface of the protrusion.
2 . The semiconductor structure according to claim 1 , further comprising:
an interlayer dielectric layer, located on the isolation layer exposed from the device gate structure, wherein the interlayer dielectric layer covers the source/drain doped layer, and fills at least part of the gap.
3 . The semiconductor structure according to claim 1 , wherein the isolation layer comprises a first isolation layer located below the device gate structure and a second isolation layer located at a side of the device gate structure, and a top surface of the second isolation layer is lower than a top surface of the first isolation layer.
4 . The semiconductor structure according to claim 1 , wherein the source/drain doped layers comprises a sidewall epitaxial layer, in contact with a sidewall of the channel structure of the protruding structures of the plurality of protruding structures below the device gate structure and a source/drain epitaxial layer, located on a sidewall of the sidewall epitaxial layer.
5 . The semiconductor structure according to claim 4 , wherein a material of the sidewall epitaxial layer comprises at least one of silicon, silicon phosphide, silicon germanium, silicon carbide, germanium, gallium nitride, gallium arsenide, or indium gallium.
6 . The semiconductor structure according to claim 1 , wherein in a direction perpendicular to a bottom wall of the source/drain doped layer, a height of the gap is in a range of 5 nm to 10 nm.
7 . The semiconductor structure according to claim 1 , wherein:
a material of the substrate comprises at least one of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, or indium gallium;
a material of the protrusion comprises at least one of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, or indium gallium; and
a material of the channel structure comprises at least one of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, or indium gallium.
8 . The semiconductor structure according to claim 1 , wherein:
the protruding structure is a fin, and the protrusion and the channel structure are an integral structure; or
the channel structure comprises one or more channel layers spaced apart and suspended on the protrusion, and the device gate structure surrounds the channel layers.
9 . The semiconductor structure according to claim 1 , wherein the device gate structure comprises a gate dielectric layer and a gate layer located on the gate dielectric layer.
10 . The semiconductor structure according to claim 9 , wherein a material of the gate dielectric layer comprises:
at least one of silicon oxide, nitrogen-doped silicon oxide, HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 , or Al 2 O 3 ; and
a material of the gate layer comprises at least one of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, or Ni.