Transistor including bottom isolation and manufacturing method thereof

1 . A method, comprising:

forming a plurality of stacked first channels of a first transistor above a semiconductor substrate;

forming a plurality of stacked second channels of a second transistor above the semiconductor substrate;

forming a plurality of inner spacers interleaved with the first channels;

depositing a dielectric layer on sidewalls of the first channels, on sidewalls of the inner spacers, and on the semiconductor substrate at a bottom of a first source/drain trench;

changing a composition of a first portion of the dielectric layer at the bottom of the trench relative to a second portion of the dielectric layer on the sidewalls of the first channels and inner spacers by performing a dopant implantation process;

forming a bottom dielectric region on the semiconductor substrate from the first portion of the dielectric layer by selectively etching, with an etching process, the second portion of the dielectric layer with respect to the first portion;

forming a first source/drain region of the first transistor in the first source/drain trench on the bottom dielectric region and coupled to the first channels; and

forming a second source/drain region of the second transistor in direct contact with the semiconductor substrate and coupled to the second channel regions.

2 . The method of claim 1 , wherein forming the bottom dielectric region includes:

depositing the dielectric layer on sidewalls of the second channels and on the semiconductor substrate at the bottom of a second source/drain trench;

entirely removing the dielectric layer from the sidewalls of the second channels and the bottom of the second source/drain trench with the etching process.

3 . The method of claim 2 , further comprising covering the dielectric layer in the second source/drain trench with a mask layer during the dopant implantation process.

4 . The method of claim 1 , wherein forming the first source/drain region includes epitaxially growing a first epitaxial feature over the semiconductor substrate, epitaxially growing a second epitaxial feature from the first channel region, and epitaxially growing a third epitaxial feature over the first epitaxial feature.

5 . The method of claim 4 , wherein forming the bottom dielectric region is after epitaxially growing the first epitaxial feature.

6 . The method of claim 1 , wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor.

7 . A method, comprising:

defining, from a first semiconductor fin, a stack of first channels of a first gate all around transistor and a stack of second channels of a second gate all around transistor by forming a first trench in the semiconductor fin;

defining, from a second semiconductor fin, a stack of third channels of a third transistor by forming a second trench in the second semiconductor fin; forming a plurality of inner spacers interleaved with first channels; depositing a dielectric layer in the first trench and the second trench;

changing a composition of a first portion of the dielectric layer at the bottom of the first trench relative to a second portion of the dielectric layer on the sidewalls of the first channels and inner spacers and in the second trench by performing a dopant implantation process;

forming, from the first portion of the dielectric layer, a bottom dielectric region at the bottom of the first trench on the semiconductor substrate by selectively etching, with an etching process, the second portion of the dielectric layer with respect to the first portion;

forming a source/drain region of the first and second gate all around transistors on the bottom dielectric region;

and forming a second source/drain region of the third gate all around transistors in direct contact with the semiconductor substrate in the second trench.

8 . The method of claim 7 , further comprising:

defining, in the second semiconductor fin, stacked fourth channels of a fourth gate all around transistor by forming the second trench in the semiconductor fin, the second source/drain region being coupled to the fourth channels.

9 . The method of claim 8 , wherein the first and second gate all around transistors are N-type transistors and the third and fourth gate all around transistors are P-type transistors.

10 . The method of claim 8 , wherein the semiconductor substrate imparts a strain to the second source/drain region.

11 . A method, comprising:

forming a plurality of first stacked channels of a first transistor of a first conductivity type above a semiconductor substrate;

forming a plurality of second stacked channels of a second transistor of a second conductivity type above the semiconductor substrate;

forming a plurality of first inner spacers interleaved with the first channels and a plurality of second inner spacers interleaved with the second channels;

depositing a dielectric layer on sidewalls of the first and second channels sidewalls of the first and second inner spacers, on the semiconductor substrate;

forming, from the dielectric layer, a bottom dielectric region on the semiconductor substrate adjacent to the first channels by:

changing a composition of a portion of the dielectric layer on the semiconductor substrate adjacent to the first channels by performing a dopant implantation process; and

removing the dielectric layer from sidewalls of the first and second channels, the sidewalls of the first and second inner spacers, and from the semiconductor substrate adjacent to the second channels;

forming a first source/drain region of the first transistor above the semiconductor substrate and separated from the semiconductor substrate by the bottom dielectric region; and

forming a second source/drain region of the second transistor in direct contact with an intrinsic semiconductor region of the semiconductor substrate adjacent to the second channels.

12 . The method of claim 11 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

13 . The method of claim 11 , wherein the bottom dielectric region and the first source/drain region are laterally bounded by a first dielectric structure and a second dielectric structure.

14 . The integrated circuit of claim 12 , wherein the semiconductor substrate imparts a strain to the second source/drain region.

15 . The integrated circuit of claim 12 , wherein a bottommost surface of the first source/drain region is higher than a bottommost surface of the second source/drain region.

16 . The integrated circuit of claim 12 , wherein the semiconductor substrate includes a topmost surface of the first source/drain region substantially planar to a topmost surface of the second source/drain region.

17 . The method of claim 11 , comprising forming a gate electrode wrapped around the first channels.

18 . The method of claim 11 , wherein a topmost surface of the bottom dielectric region is above a topmost surface of the semiconductor substrate and a bottommost surface of the bottom dielectric region is lower than the topmost surface of the semiconductor substrate.

19 . The method of claim 11 , wherein the bottom dielectric region is between 2 nm and 10 nm thick.

20 . The method of claim 11 , wherein the bottom dielectric region includes a doped silicon nitride.