Enabling anneal for reliability improvement and multi-VT with interfacial layer regrowth suppression

1 . A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising:

a first gate-all-around field-effect transistor (GAA FET) device having a first Vt disposed on a first region of a substrate, the first GAA FET device including:

a plurality of first channels;

an interfacial layer around each of the plurality of the first channels;

a dielectric layer around the interfacial layer;

a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric laver; and

a first work function metal between each adjacent pair of the plurality of first channels; and

a second GAA FET device having a second Vt different from the first Vt disposed on a second region of the substrate, the second GAA FET device including:

a plurality of second channels with no dipole layer around them;

a second work function metal between each adjacent pair of the plurality of second channels; and

the first work function metal on the second work function metal.

2 . The semiconductor device of claim 1 , wherein the plurality of first channels are nanosheets, and the plurality of second channels are nanosheets.

3 . The semiconductor device of claim 2 , further comprising an isolator layer on the substrate, wherein the isolator layer separates the first work function metal and the second work function metal from the substrate.

4 . The semiconductor device of claim 3 , further comprising a gate electrode on and in electrical contact with the first work function metal.

5 . The semiconductor device of claim 4 , further comprising another dipole layer on the isolator layer.

6 . The semiconductor device of claim 5 , wherein the isolator layer is hafnium silicate.

7 . The semiconductor device of claim 5 , wherein the first GAA FET device is an n-type FET (nFET) and the second GAA FET device is a p-type FET (pFET).

8 . The semiconductor device of claim 5 , wherein the first GAA FET device is a p-type FET (pFET) and the second GAA FET device is an n-type FET (nFET).

9 . The semiconductor device of claim 5 , wherein the first work function metal is titanium nitride (TiN).

10 . The semiconductor device of claim 9 , wherein the second work function metal is tantalum nitride (TaN).

11 . A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising;

a first gate-all-around field-effect transistor (GAA FET) device disposed on a base structure in a first region and associated with a first Vt, the first GAA FET device including:

a plurality of first channels;

an interfacial layer around each of the plurality of the first channels;

a dielectric layer around the interfacial layer;

a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric layer; and

a first work function metal pinching off gaps between the plurality of first channels;

a second GAA FET device disposed on the base structure in a second region and associated with a second Vt, the second GAA FET device including:

a plurality of second channels with no dipole layer around them;

a second work function metal pinching off gaps between the plurality of second channels; and

the first work function metal on the second work function metal; and

a gate electrode on the first work function metal.

12 . The device of claim 11 , wherein the plurality of first channels and the plurality of second channels are nanosheets, and wherein the base structure includes an isolator layer on a substrate.

13 . The device of claim 11 , wherein the first GAA FET device is an n-type FET (nFET) and the second GAA FET device is a p-type FET (pFET).

14 . The device of claim 11 , wherein the first GAA FET device is a p-type FET (pFET) and the second GAA FET device is an n-type FET (nFET).

15 . A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising:

a first gate-all-around field-effect transistor (GAA FET) device disposed on a base structure in a first region and associated with a first Vt, the first GAA FET device including:

a plurality of first channels;

an interfacial layer around each of the plurality of first channels;

a dielectric layer around the interfacial layer;

a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric layer;

a first barrier layer on the dipole layer;

a scavenging metal layer on the first barrier layer;

a wetting layer on the scavenging metal layer around the plurality of first channels; and

a first work function metal between each adjacent pair of the plurality of first channels; and

a second GAA FET device disposed on the base structure in a second region and associated with a second Vt, the second GAA FET device including:

a plurality of second channels with no dipole layer around them;

a second barrier layer on the plurality of second channels;

the scavenging metal layer on the second barrier layer;

the wetting layer on the scavenging metal layer;

a gate electrode on the wetting layer;

a second work function metal between each adjacent pair of the plurality of second channels; and

the first work function metal on the second work function metal.

16 . The device of claim 15 , wherein the plurality of first channels and the plurality of second channels include nanosheets, and wherein the base structure includes an isolator layer on a substrate.

17 . The device of claim 15 , wherein the first GAA FET device includes an n-type FET (nFET) and the second GAA FET device includes a p-type FET (pFET).

18 . The device of claim 15 , wherein the first GAA FET device includes a p-type FET (pFET) and the second GAA FET device includes an n-type FET (nFET).

19 . The device of claim 15 , further comprising a cap layer disposed between the wetting layer and the scavenging metal layer.