Semiconductor device including gate structure and multiple integrated separation structures

1 . A semiconductor device comprising:

active regions, including a first active region and a second active region parallel to each other, disposed on a substrate and extends in a first horizontal direction;

an isolation region defining the active regions;

a gate structure disposed on the isolation region and extending in a second horizontal direction to intersect an active region; and

a plurality of channel layers spaced apart from each other and disposed on the active region in a vertical direction, perpendicular to the first horizontal direction and the second horizontal direction; and

separation structures penetrating through the gate structure and disposed on the isolation region between the first active region and the second active region,

wherein the separation structures include a first separation structure extending into the isolation region,

wherein an uppermost portion of the first separation structure is disposed on a level higher than a level of an uppermost portion of the isolation region,

and a second separation structure disposed on the first separation structure and penetrating through at least a portion of the first separation structure, the second separation structure having a lowermost portion disposed at a level equal to or lower than a lower surface of a lowermost one of the plurality of channel layers and extending into the first separation structure,

wherein the lowermost portion of the second separation structure is disposed on a level higher than a level of an upper surface of the isolation region adjacent to the first separation structure, and

wherein a width of a lower region of the second separation structure in the second horizontal direction is less than a width of an upper region of the first separation structure in the second horizontal direction.

2 . The semiconductor device of claim 1 , wherein

a first distance from a first height level of a lower surface of the gate structure, vertically overlapping the isolation region adjacent to the first separation structure, to a second height level of a lower end of the first separation structure is greater than a second distance from the first height level of the lower surface of the gate structure to a third height level of an upper end of the first separation structure.

3 . The semiconductor device of claim 1 , wherein the plurality of channel layers contacts source/drain regions, and

wherein the uppermost portion of the first separation structure is disposed on a level lower than a midpoint level between the upper surface of the isolation region and an upper surface of an uppermost channel layer among the plurality of channel layers.

4 . The semiconductor device of claim 3 , further comprising:

an insulating structure penetrating through the plurality of channel layers and at least a portion of the active regions.

5 . The semiconductor device of claim 1 , wherein

the first separation structure and the second separation structure include substantially a same insulating material.

6 . The semiconductor device of claim 1 , wherein

the first separation structure and the second separation structure include different insulating materials.

7 . The semiconductor device of claim 1 , wherein

the first separation structure includes a first region vertically overlapping the gate structure and a second region vertically overlapping the second separation structure.

8 . The semiconductor device of claim 1 , wherein

the gate structure includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer.

9 . The semiconductor device of claim 8 , wherein

at least a portion of a side surface of the second separation structure contacts the gate electrode.

10 . A semiconductor device comprising:

active regions, including a first active region and a second active region parallel to each other, disposed on a substrate and extends in a first horizontal direction;

an isolation region between the first active region and the second active region;

a first gate structure intersecting the first active region, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a first end portion disposed on the isolation region;

a second gate structure intersecting the second active region, extending in the second horizontal direction, and having a second end portion opposite from the first end portion of the first gate structure disposed on the isolation region;

a first separation structure vertically penetrating through at least a portion of the isolation region;

wherein an uppermost portion of the first separation structure is disposed on a level higher than a level of an upper surface of the isolation region; and

a second separation structure disposed between the first end portion of the first gate structure and the second end portion of the second gate structure and contacting the first separation structure, the second separation structure having a lowermost portion disposed at a level equal to or lower than a lower surface of a lowermost one of a plurality of channel layers and extending into the first separation structure,

wherein the lowermost portion of the second separation structure is disposed on a level higher than a level of an upper surface of the isolation region adjacent to the first separation structure,

wherein the first gate structure includes a first gate dielectric layer and a first gate electrode disposed on the first gate dielectric layer,

wherein the second gate structure includes a second gate dielectric layer and a second gate electrode disposed on the second gate dielectric layer,

wherein a maximum width of the second separation structure in the second horizontal direction is less than a minimum width of the first separation structure in the second horizontal direction,

wherein the first separation structure is spaced apart from the first gate electrode and the second gate electrode, and

wherein the second separation structure contacts the first gate electrode and the second gate electrode.

11 . The semiconductor device of claim 10 , wherein

a first distance between an upper surface of the first separation structure and a lower surface of the first separation structure is less than a second distance between an upper surface of the second separation structure and a lower surface of the second separation structure.

12 . The semiconductor device of claim 10 , wherein

at least a portion of an upper surface of the first separation structure has a convex shape in a direction away from an upper surface of the substrate.

13 . The semiconductor device of claim 10 , wherein

at least a portion of an upper surface of the first separation structure has a convex shape in a direction toward an upper surface of the substrate.

14 . A semiconductor device comprising:

active regions, including a first active region and a second active region parallel to each other, disposed on a substrate and extends in a first horizontal direction;

an isolation region between the first active region and the second active region;

a first separation structure vertically penetrating through at least a portion of the isolation region;

wherein an uppermost portion of the first separation structure is disposed on a level higher than a level of an upper surface of the isolation region;

first channel layers spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, disposed on the first active region;

second channel layers spaced apart from each other in the vertical direction disposed on the second active region;

a second separation structure having a lowermost portion disposed at a level equal to or lower than a lower surface of a lowermost one of the first channel layers and the second channel layers and extending into the first separation structure;

wherein the lowermost portion of the second separation structure is disposed on a level higher than a level of an upper surface of the isolation region adjacent to the first separation structure;

a first gate structure intersecting the first active region and the first channel layers, surrounding each of the first channel layers, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a first end portion disposed on an upper surface of the first separation structure; and

a second gate structure intersecting the second active region and the second channel layers, surrounding each of the second channel layers, extending in the second horizontal direction, and having a second end portion disposed on an upper surface of the first separation structure,

wherein the first gate structure includes a first gate dielectric layer and a first gate electrode disposed on the first gate dielectric layer, and

wherein the second gate structure includes a second gate dielectric layer and a second gate electrode disposed on the second gate dielectric layer.

15 . The semiconductor device of claim 14 , wherein

the first gate electrode and the second gate electrode contact each other on the first separation structure,

wherein the first gate dielectric layer includes a portion interposed between the first gate electrode and the first separation structure, and

wherein the second gate dielectric layer includes a portion interposed between the second gate electrode and the first separation structure.

16 . The semiconductor device of claim 14 , further comprising:

the second separation structure disposed between the first end portion of the first gate structure and the second end portion of the second gate structure and contacts the first separation structure.