Field-effect transistors (FETs) employing thermal expansion of work function metal layers for strain effect and related fabrication methods
Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.
1 . A three-dimensional (3D) field-effect transistor (FET) structure, comprising:
at least one semiconductor slab, each comprising a first face and a second face opposite to the first face;
a dielectric layer disposed on the first face and the second face in a channel region of the at least one semiconductor slab;
a work function metal layer comprising a work function metal disposed on the dielectric layer; and
a gate comprising a gate material disposed on the work function metal layer;
wherein:
the channel region of each of the at least one semiconductor slab is configured to conduct current in a first direction; and
the work function metal layer is configured to cause a first force on the channel region of the at least one semiconductor slab in the first direction.
2 . The 3D FET structure of claim 1 , wherein the at least one the work function metal is a different material than the gate material.
3 . The 3D FET structure of claim 1 , wherein the work function metal layer is further configured to cause a second force to be exerted on the channel region in a second direction orthogonal to the first direction.
4 . The 3D FET structure of claim 1 , wherein:
the at least one semiconductor slab is doped with a trivalent dopant; and
the work function metal layer configured to cause the first force is configured to cause a tensile force to be exerted on the channel region in the first direction.
5 . The 3D FET structure of claim 4 , wherein the work function metal has a work function in a range of 4.0 to 4.25 electron volts (eV).
6 . The 3D FET structure of claim 4 , wherein the work function metal comprises manganin nitride (MnN) and the gate material comprises one of aluminum and tungsten.
7 . The 3D FET structure of claim 1 , wherein:
the at least one semiconductor slab is doped with a pentavalent dopant; and
the work function metal layer configured to cause the first force is configured to cause a compressive force to be exerted on the channel region in the first direction.
8 . The 3D FET structure of claim 7 , wherein the work function metal has a work function in a range of 4.5 to 5.5 electron volts (eV).
9 . The 3D FET structure of claim 7 , wherein the work function metal comprises one of silver (Ag), iron nitride (FeN), and nickel aluminum (NiAl) and the gate material comprises one of aluminum and tungsten.
10 . The 3D FET structure of claim 7 , the work function metal layer comprising:
a first work function metal layer comprising one of silver (Ag), iron nitride (FeN), and nickel aluminum (NiAl); and
a second work function metal layer comprising manganin nitride (MnN).
11 . The 3D FET structure of claim 7 , wherein the work function metal does not comprise titanium (Ti) aluminum (Al) (TiAl).
12 . The 3D FET structure of claim 1 , comprising:
a first thickness of the work function metal layer is less than 2 nanometers (nm); and
a second thickness of the gate material disposed on the work function metal layer is at least 50 nm.
13 . The 3D FET structure of claim 1 , comprising one of titanium nitride (TiN) layer and a tantalum nitride (TaN) layer between the work function metal and the dielectric layer.
14 . The 3D FET structure of claim 1 , wherein the 3D FET structure comprises one of a gate-all-around FET, a fork-sheet FET, and a complementary FET.
15 . The 3D FET structure of claim 1 , integrated into an integrated circuit.
16 . The 3D FET structure of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
17 . A three-dimensional (3D) complementary field-effect transistor (FET) (CFET) structure comprising:
a first type FET comprising:
at least one first semiconductor slab each comprising a first face and a second face opposite to the first face;
a first dielectric layer disposed on the first face and the second face in a channel region of the at least one first semiconductor slab;
a first work function metal layer comprising a first work function metal disposed on the first dielectric layer; and
a first gate comprising a gate material disposed on the first work function metal layer; and
a second type FET comprising:
at least one second semiconductor slab each comprising a third face and a fourth face opposite to the third face;
a second dielectric layer disposed on the third face and the fourth face in a channel region of the at least one second semiconductor slab;
a second work function metal layer comprising a second work function metal disposed on the second dielectric layer; and
a second gate comprising the gate material disposed on the second work function metal layer;
wherein:
the first work function metal layer is configured to cause a tensile force on the channel region of the at least one first semiconductor slab; and
the second work function metal layer is configured to cause a compressive force on the channel region of the at least one second semiconductor slab.
18 . The 3D CFET structure of claim 17 , comprising one of a gate-all-around FET and a fork-sheet FET.
19 . The 3D CFET structure of claim 17 , wherein the gate material is different than the first work function metal and the second work function metal.
20 . The 3D CFET structure of claim 17 , wherein:
the first work function metal has a work function in a range of 4.0 to 4.25 electron volts (eV); and
the second work function metal has a work function in a range of 4.5 to 5.5 eV.
21 . The 3D CFET structure of claim 17 , wherein:
the first work function metal comprises manganin nitride (MnN); and
the second work function metal comprises one of silver (Ag), iron nitride (FeN), and nickel aluminum (NiAl).
22 . The 3D CFET structure of claim 17 , the second work function metal layer comprising:
a third work function metal layer comprising one of silver (Ag), iron nitride (FeN), and nickel aluminum (NiAl); and
a fourth work function metal layer comprising manganin nitride (MnN).
23 . A method of fabricating a complementary three-dimensional (3D) field-effect transistor (FET) structure comprising:
forming at least one semiconductor slab, each comprising a first face and a second face opposite to the first face;
forming a dielectric layer disposed on the first face and the second face in a channel region of the at least one semiconductor slab;
forming a work function metal layer comprising a work function metal disposed on the dielectric layer; and
forming a gate comprising a gate material disposed on the work function metal layer;
wherein:
the channel region of each of the at least one semiconductor slab is configured to conduct current in a first direction; and
the work function metal layer causes a force on the channel region of the at least one semiconductor slab in the first direction.