Semiconductor device having a separation structure
A semiconductor device may include: a substrate; a lower pattern extending from the substrate in a first direction; a channel pattern disposed on the lower pattern; a source/drain pattern disposed on sides of the channel pattern; a first gate structure and a second gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern; and a separation structure disposed between the first gate structure and the second gate structure, and including a first portion extending in the first direction and a second portion protruding from the first portion toward the channel pattern, wherein the first gate structure includes first and second conductive patterns stacked sequentially from the respective portion of the channel pattern, and a length of the second conductive pattern in the second direction is equal to or greater than a length of the second portion in the second direction.
1 . A semiconductor device, comprising:
a substrate;
a lower pattern extending from the substrate in a first direction;
a channel pattern disposed on the lower pattern;
a source/drain pattern disposed on sides of the channel pattern;
a first gate structure and a second gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern; and
a separation structure disposed between the first gate structure and the second gate structure, and including a first portion extending in the first direction and a second portion protruding from the first portion toward the channel pattern,
wherein the first gate structure includes a first conductive pattern and a second conductive pattern stacked sequentially from the respective portion of the channel pattern, and
a length of the second conductive pattern in the second direction is equal to or greater than a length of the second portion of the separation structure in the second direction.
2 . The semiconductor device of claim 1 , wherein the first conductive pattern is spaced apart from the first portion of the separation structure.
3 . The semiconductor device of claim 2 , wherein a length in the second direction between the first portion of the separation structure and the first conductive pattern is shorter than a length in the second direction between the first portion of the separation structure and the channel pattern.
4 . The semiconductor device of claim 1 , wherein a length of the first conductive pattern in the second direction is shorter than a length in the second direction between the channel pattern and the first portion of the separation structure.
5 . The semiconductor device of claim 1 , wherein the second portion of the separation structure is located between the first conductive pattern and the first portion of the separation structure.
6 . The semiconductor device of claim 5 , wherein at least a portion of a side surface of the second conductive pattern overlaps the second portion of the separation structure in the first direction.
7 . The semiconductor device of claim 1 , wherein the second gate structure includes a third conductive pattern and a fourth conductive pattern stacked sequentially from the respective portion of the channel pattern, and
a distance between the first conductive pattern and the third conductive pattern is greater than a distance between the second conductive pattern and the fourth conductive pattern.
8 . The semiconductor device of claim 1 , wherein in a plan view, the first conductive pattern surrounds at least a portion of the second conductive pattern.
9 . The semiconductor device of claim 8 , wherein the first conductive pattern comprises a protrusion that overlaps at least a portion of the second conductive pattern in the first direction.
10 . The semiconductor device of claim 1 , further comprising a gate spacer located between the source/drain pattern and the first gate structure,
wherein the second portion of the separation structure is disposed between the gate spacer and the second conductive pattern.
11 . The semiconductor device of claim 10 , wherein the first gate structure further includes a gate dielectric layer interposed between the first conductive pattern and the channel pattern, and between the first conductive pattern and the gate spacer.
12 . The semiconductor device of claim 11 , wherein the gate dielectric layer extends along a side surface of the second portion of the separation structure.
13 . The semiconductor device of claim 11 , further comprising a field insulation layer located on a side surface of the lower pattern,
wherein the first portion of the separation structure is located on the field insulation layer, and the second portion of the separation structure is located on the second conductive pattern.
14 . A semiconductor device, comprising:
a substrate;
a lower pattern disposed on the substrate and extending in a first direction;
a channel pattern disposed on the lower pattern;
a source/drain pattern disposed on sides of the channel pattern; and
a first gate structure and a second gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern,
wherein the first gate structure includes a first conductive pattern and a second conductive pattern stacked sequentially from the respective portion of the channel pattern,
the second gate structure includes a third conductive pattern and a fourth conductive pattern stacked sequentially from the respective portion of the channel pattern, and
a distance between the first conductive pattern and the third conductive pattern is greater than a distance between the second conductive pattern and the fourth conductive pattern.
15 . The semiconductor device of claim 14 , further comprising a gate spacer located between the source/drain pattern and the first gate structure,
wherein at least a portion of the first conductive pattern is disposed between the gate spacer and the second conductive pattern.
16 . The semiconductor device of claim 15 , wherein at least a portion of the first conductive pattern overlaps the second conductive pattern in the first direction.
17 . The semiconductor device of claim 15 , wherein the first gate structure further includes a gate dielectric layer interposed between the first conductive pattern and the channel pattern, and between the first conductive pattern and the gate spacer.
18 . The semiconductor device of claim 17 , wherein the gate dielectric layer extends along a side surface of the gate spacer.
19 . A semiconductor device, comprising:
a substrate;
a lower pattern disposed on the substrate and extending in a first direction;
a channel pattern disposed on the lower pattern;
a source/drain pattern disposed on sides of the channel pattern; and
a first gate structure extending in a second direction intersecting the first direction and surrounding respective portions of the channel pattern,
wherein the first gate structure includes a first conductive pattern and a second conductive pattern stacked sequentially from the channel pattern,
a separation structure interposed within a recess of the first conductive pattern, and
at least a portion of the second conductive pattern is surrounded by the separation structure.
20 . The semiconductor device of claim 19 , further comprising a field insulation layer located on a side surface of the lower pattern,
wherein the separation structure is located on the field insulation layer.