Transistor device with multi-layer channel structure
An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.
1 . A method for forming an integrated chip, the method comprising:
depositing an insulator layer over a base dielectric layer;
depositing a first channel layer over the insulator layer, the first channel layer comprising a first semiconductor having a first carrier concentration;
depositing a first dielectric layer over the first channel layer;
etching the first dielectric layer and the first channel layer to form a trench in the first dielectric layer and the first channel layer, wherein the trench is delimited by sidewalls of the first dielectric layer, sidewalls of the first channel layer, and an upper surface of the insulator layer;
depositing a second channel layer in the trench along the sidewalls of the first dielectric layer, along the sidewalls of the first channel layer, and along the upper surface of the insulator layer, the second channel layer comprising a second semiconductor having a second carrier concentration, different from the first carrier concentration;
depositing a third channel layer in the trench along sidewalls and an upper surface of the second channel layer;
performing a planarization process on the third channel layer, the second channel layer, and the first dielectric layer; and
forming a pair of source/drains directly over the first channel layer.
2 . The method of claim 1 , wherein the planarization process removes the first dielectric layer from over the first channel layer and uncovers a pair of top surfaces of the first channel layer, and wherein the pair of source/drains are formed on the pair of top surfaces of the first channel layer.
3 . The method of claim 1 , wherein the third channel layer comprises a third semiconductor having a third carrier concentration, different from the first carrier concentration and the second carrier concentration, wherein the first semiconductor comprises a first metal-oxide having a first metal ratio, wherein the second semiconductor comprises a second metal-oxide having a second metal ratio, less than the first metal ratio, and wherein the third semiconductor comprises a third metal-oxide having a third metal ratio, less than the second metal ratio.
4 . The method of claim 1 , further comprising:
forming a first gate layer over the base dielectric layer, wherein the insulator layer is formed over the first gate layer; and
etching the first channel layer to remove the first channel layer from a periphery of the insulator layer before depositing the first dielectric layer over the first channel layer.
5 . The method of claim 1 , further comprising:
depositing a second dielectric layer in the trench and over the third channel layer to fill the trench before the performing the planarization process.
6 . The method of claim 4 , further comprising:
depositing a second dielectric layer on the third channel layer, the second channel layer, and the first dielectric layer; and
etching the second dielectric layer to form a pair of source/drain openings in the second dielectric layer and to uncover the first channel layer, wherein the pair of source/drains are formed directly over the first channel layer after etching the second dielectric layer by depositing a conductive layer in the pair of source/drain openings and on the first channel layer.
7 . The method of claim 6 , further comprising:
etching the second dielectric layer to form a gate opening in the second dielectric layer between the pair of source/drains and to uncover the third channel layer; and
depositing a second gate layer in the gate opening and on the third channel layer.
8 . A method for forming an integrated chip, the method comprising:
depositing a first gate layer to form a first gate electrode over a base dielectric layer;
depositing an insulator layer over the first gate electrode;
depositing a first channel layer comprising a first semiconductor over the insulator layer;
etching the first channel layer to separate a first portion of the first channel layer and a second portion of the first channel layer and to uncover an upper surface of the insulator layer between the first and second portions of the first channel layer;
depositing a second channel layer comprising a second semiconductor between the first and second portions of the first channel layer, along a sidewall of the first portion of the first channel layer, along the upper surface of the insulator layer, and along a sidewall of the second portion of the first channel layer;
depositing a third channel layer comprising a third semiconductor between the first and second portions of the first channel layer, along sidewalls of the second channel layer, and along an upper surface of the second channel layer; and
forming a first source/drain electrode on the first portion of the first channel layer and forming a second source/drain electrode on the second portion of the first channel layer.
9 . The method of claim 8 , wherein a dielectric layer is between the first source/drain electrode and the second source/drain electrode, the method further comprising:
etching the dielectric layer to uncover a portion of the third channel layer and a portion of the second channel layer; and
depositing a second gate layer to form a second gate electrode on the portion of the third channel layer, on the portion of the second channel layer, and laterally between the first and second source/drain electrodes.
10 . The method of claim 9 , wherein the etching of the dielectric layer recesses the third channel layer and the second channel layer, and wherein a bottom surface of the second gate electrode is below a top surface of the second channel layer and below a top surface of the first channel layer.
11 . The method of claim 10 , wherein a top surface of the third channel layer is below the top surface of the second channel layer and below the top surface of the first channel layer.
12 . A method of forming an integrated chip, the method comprising:
forming a first gate electrode;
forming an insulator layer on the first gate electrode;
forming a first portion and a second portion of a first channel layer laterally spaced apart on an upper surface of the insulator layer;
forming a second channel layer on the upper surface of the insulator layer and between the first and second portions of the first channel layer;
forming a third channel layer over the second channel layer and between the first and second portions of the first channel layer, wherein the second channel layer laterally surrounds the third channel layer in a ring-shaped, closed path; and
forming a first source/drain electrode on the first portion of the first channel layer and forming a second source/drain electrode on the second portion of the first channel layer.
13 . The method of claim 12 , wherein the first channel layer comprises a first semiconductor having a first carrier concentration, wherein the second channel layer comprises a second semiconductor having a second carrier concentration less than the first carrier concentration, and wherein the third channel layer comprises a third semiconductor having a third carrier concentration less than the second carrier concentration.
14 . The method of claim 12 , wherein the second channel layer extends laterally from the first portion of the first channel layer to the second portion of the first channel layer, and wherein the second channel layer separates the third channel layer from the first and second portions of the first channel layer.
15 . The method of claim 12 , wherein the third channel layer is directly between sidewalls of the first channel layer, directly over the second channel layer, and directly between sidewalls of the second channel layer.
16 . The method of claim 12 , further comprising:
forming a second gate electrode over the third channel layer and laterally spaced between the first and second source/drain electrodes.
17 . The method of claim 16 , wherein the third channel layer is between a lower surface of the second gate electrode and an upper surface of the second channel layer.
18 . The method of claim 12 , wherein the insulator layer comprises a dielectric having a dielectric constant greater than a dielectric constant of silicon dioxide.
19 . The method of claim 12 , wherein the insulator layer comprises a ferroelectric.
20 . The method of claim 12 , wherein the first portion and the second portion of the first channel layer contact the upper surface of the insulator layer, and wherein the second channel layer contacts the upper surface of the insulator layer between the first and second portions of the first channel layer.